Method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance

Abstract

A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

We claim: 
     
         1 . A method for determining an integrated circuit layout comprising:
 generating at least one memory instance in dependence on a memory architecture, at least one first property associated with said memory instance, and at least once second property associated with a standard cell library; and   generating, having regard to a logical representation of said integrated circuit, said integrated circuit layout by combining said at least one memory instance with at least one standard cell of said standard cell library.   
     
     
         2 . A method as claimed in  claim 1  wherein a height of said at least one memory instance is dependent on said at least one second property of said standard cell library. 
     
     
         3 . A method as claimed in  claim 2  wherein said at least one second property of said standard cell library is a standard cell row height. 
     
     
         4 . A method as claimed in  claim 3  wherein said height of said at least one memory instance is a multiple of said standard cell row height. 
     
     
         5 . A method as claimed in  claim 1  wherein said at least one second property of said standard cell library is a requirement that standard cells of the standard cell library must abut against an edge of the memory instance within the integrated circuit layout. 
     
     
         6 . A method as claimed in  claim 5 , wherein said standard cell library includes one or more abutment standard cells for use as the standard cells to abut against said edge of the memory instance. 
     
     
         7 . A method as claimed in  claim 1  wherein said generating said integrated circuit layout further comprises:
 populating at least one standard cell row extending in a first direction with standard cells selected from said standard cell library during the generation of said standard cell layout. 
 
     
     
         8 . A non-transitory storage medium providing a computer program for controlling a computer to perform the method of  claim 1 . 
     
     
         9 . An integrated circuit comprising:
 at least one memory instance, said at least one memory instance having a first property; and   at least one standard cell of a standard cell library, said standard cell library having a second property;   wherein said at least one memory instance is configured having regard to both said first and second properties.   
     
     
         10 . An integrated circuit layout comprising:
 a configuration of at least one memory instance, said at least one memory instance having a first property; and   at least one standard cell of a standard cell library, said standard cell having a second property;   wherein said configuration of said at least one memory instance is dependent on said first and second properties.