Semiconductor devices employing high-k dielectric layers as a gate insulating layer

Abstract

A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided.

1 .- 9 . (canceled) 
     
     
         10 . A semiconductor device comprising:
 a semiconductor substrate having a first region and a second region;   a first gate pattern on one predetermined region of the semiconductor substrate in the first region; and   a second gate pattern on another predetermined region of the semiconductor substrate in the second region,   wherein the first gate pattern includes a first nitrogen-containing lower gate insulating layer pattern and a first metal gate electrode which are sequentially stacked, and   wherein the second gate pattern includes a second nitrogen-containing lower gate insulating layer pattern, a second upper gate insulating layer pattern and a second metal gate electrode which are sequentially stacked.   
     
     
         11 . The semiconductor device as claimed in  claim 10 , wherein each of the first and second nitrogen-containing lower gate insulating layer patterns includes a nitrogen-containing high-k dielectric layer. 
     
     
         12 . The semiconductor device as claimed in  claim 11 , wherein the nitrogen-containing high-k dielectric layer includes a nitrified metal oxide layer or a nitrified metal silicate layer. 
     
     
         13 . The semiconductor device as claimed in  claim 10 , wherein the second upper gate insulating layer pattern includes a nitrogen-containing high-k dielectric layer or a nitrogen-free high-k dielectric layer. 
     
     
         14 . The semiconductor device as claimed in  claim 13 , wherein the second upper gate insulating layer pattern is a nitrogen-containing high-k dielectric layer and a nitrogen concentration of the second upper gate insulating layer is lower than that of the second nitrogen-containing lower gate insulating layer pattern. 
     
     
         15 . The semiconductor device as claimed in  claim 10 , wherein the first metal gate electrode is formed of a same metal layer as the second metal gate electrode. 
     
     
         16 . The semiconductor device as claimed in  claim 10 , wherein the first gate pattern further includes a first upper gate insulating layer pattern between the first nitrogen-containing lower gate insulating layer pattern and the first metal gate electrode, the first upper gate insulating layer pattern is formed of a same material layer as the second upper gate insulating layer pattern, and the first upper gate insulating layer pattern is thinner than the second upper gate insulating layer pattern. 
     
     
         17 - 19 . (canceled)