Substrate inductive device methods and apparatus

Abstract

An improved low cost and highly consistent inductive apparatus. In one embodiment, the low cost and highly consistent inductive apparatus addresses concerns with so called conductive anodic filament (CAF) that occurs within these laminate structures by incorporating surface mountable chip chokes in the underlying circuit design, These conditions that result in undesirable CAF include high humidity, high bias voltage (i.e. a large voltage differential), high-moisture content, surface and resin ionic impurities, glass to resin bond weakness and exposure to high assembly temperatures that can occur, for example, during lead free solder bonding application. Methods of manufacturing and using the aforementioned substrate inductive devices are also disclosed.

What is claimed is: 
     
         1 . A substrate inductive device, comprising:
 a plurality of substrates, at least one of the substrates including a plurality of chip choke components, the chip choke components allowing for the use of larger toroidal cores than would be possible absent the incorporation of the chip choke components.   
     
     
         2 . The substrate inductive device of  claim 1 , wherein the substrate inductive device comprises a power over Ethernet (PoE) circuit comprising four (4) chip choke components and five (5) ferrite toroids. 
     
     
         3 . The substrate inductive device of  claim 2 , wherein the chip choke components comprise two-wire surface mountable chip choke components. 
     
     
         4 . The substrate inductive device of  claim 2 , wherein the chip choke components comprise three-wire surface mountable chip choke components. 
     
     
         5 . The substrate inductive device of  claim 4 , wherein the three-wire surface mountable chip choke components are configured to resolve situations in which a net magnetic flux across the chip choke component comprises a non-zero value. 
     
     
         6 . The substrate inductive device of  claim 2 , wherein the use of the four (4) chip choke components allows for a reduction in a number of turns required for the five (5) ferrite toroids. 
     
     
         7 . The substrate inductive device of  claim 6 , wherein the five (5) ferrite toroids comprise four (4) transformers and a PoE choke ferrite toroid. 
     
     
         8 . The substrate inductive device of  claim 7 , wherein the four (4) transformers each comprise ten (10) turns and the PoE choke ferrite toroid comprises eleven (11) turns. 
     
     
         9 . The substrate inductive device of  claim 8 , wherein each of the plurality of turns comprises a conductive wire inserted into a pair of through hole vias. 
     
     
         10 . A method of manufacturing a substrate inductive device, comprising:
 routing and printing a pair of printed circuit boards;   placing a plurality of surface mountable chip chokes on one of the printed circuit boards;   placing a plurality of ferrite cores on at least one of the printed circuit boards; and   routing a plurality of conductive wires around the plurality of ferrite cores by inserting the conductive wires into a plurality of through hole vias located on the pair of printed circuit boards.   
     
     
         11 . The method of manufacturing a substrate inductive device of  claim 10 , wherein the substrate inductive device comprises a power over Ethernet (PoE) circuit comprising four (4) surface mountable chip chokes and five (5) ferrite cores. 
     
     
         12 . The method of manufacturing a substrate inductive device of  claim 11 , wherein the use of the four (4) surface mountable chip chokes allows for a reduction in a number of turns required for the five (5) ferrite cores. 
     
     
         13 . The method of manufacturing a substrate inductive device of  claim 12 , wherein the five (5) ferrite cores comprise four (4) transformers and a PoE choke ferrite core. 
     
     
         14 . The method of manufacturing a substrate inductive device of  claim 13 , wherein the four (4) transformers each comprise ten (10) turns and the PoE choke ferrite core comprises eleven (11) turns. 
     
     
         15 . A substrate inductive device, comprising:
 a plurality of substrates comprising a plurality of ferrite cores, at least one of the substrates including a plurality of chip choke components, the chip choke components configured to reduce the occurrence of conductive anodic filament (CAP) formation.   
     
     
         16 . The substrate inductive device of  claim 15 , further comprising a plurality of through holes with respective conductive wires configured to be inserted into the plurality of through holes. 
     
     
         17 . The substrate inductive device of  claim 16 , wherein the inclusion of the plurality of chip choke components increases the through hole to through hole distance versus if these plurality of chip choke components were replaced with ferrite cores. 
     
     
         18 . The substrate inductive device of  claim 17 , wherein the chip choke components comprise two-wire surface mountable chip choke components. 
     
     
         19 . The substrate inductive device of  claim 17 , wherein the chip choke components comprise three-wire surface mountable chip choke components. 
     
     
         20 . The substrate inductive device of  claim 19 , wherein the three-wire surface mountable chip choke components are configured to resolve situations in which a net magnetic flux across the chip choke component comprises a non-zero value.