Twin MONOS Array for High Speed Application

Abstract

A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

What is claimed is: 
     
         1 . A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprising:
 said control gates arrayed in polysilicon control gate lines on sidewalls of said word gates arrayed in polysilicon word gate lines wherein said word gate lines and said control gate lines run in parallel wherein said word gate lines are widened in a stitch area to place a word gate contact;   an extension connecting a pair of said control gate lines between adjacent said word gate lines in a row perpendicularly to place a control gate contact wherein said extension is separated from adjacent said extension on said word gate line in between wherein said control gate contact connects to a metal line;   a salicidation block to cover said extensions and surrounding said word gate lines in said stitch area to protect them from salicidation; and   a pair of word gate contacts bridging over said salicidation block with a metal line on every other said word gate line.   
     
     
         2 . A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprising:
 said control gates arrayed in polysilicon control gate lines on sidewalls of said word gates arrayed in polysilicon word gate lines wherein said word gate lines and said control gate lines run in parallel;   an extension connecting each pair of said control gate lines in a space between adjacent said word gate lines on which to place a control gate contact wherein said extensions are placed in a zigzag pattern in two rows perpendicularly and wherein each said extension is separated from adjacent said extension on said word gate line in between;   a salicidation block to cover said extensions and surrounding said word gate lines in said stitch area to protect them from salicidation;   a control gate contact on said extension to connect to a metal line; and   a pair of word gate contacts bridging over said salicidation block with a metal line on every said word gate line.   
     
     
         3 . The stitch area configuration according to  claim 2  wherein alternate said extensions are connected to a common driver to allow “multi CG drive” wherein several control gates are driven by one control gate driver. 
     
     
         4 . A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprising:
 said control gates arrayed in control gate lines on sidewalls of said word gates arrayed in word gate lines wherein said word gate lines and said control gate lines run in parallel;   an extension connecting each pair of said control gate lines in a space between adjacent said word gate lines to place a control gate contact wherein said extensions are placed in a zigzag pattern and wherein each said extension is separated from adjacent said extension on said word gate line in between;   a control gate poly contact on said extension to connect to a metal line; and   a word gate contact between said zigzag control gate contacts on every said word gate line in a row.   
     
     
         5 . The stitch area configuration according to  claim 4  wherein alternate said extensions are connected to a common driver to allow “multi CG drive” wherein several control gates are driven by one control gate driver. 
     
     
         6 . An EEPROM semiconductor memory device comprising:
 a memory array comprising word lines, control gates, and bit lines;   word line and control gate decoders and drivers;   a bit line decoder;   a bit line control circuit; and   a chip controller to control said memory array.   
     
     
         7 . The EEPROM semiconductor memory device according to  claim 6  wherein said memory array is a twin MONOS metal bit array. 
     
     
         8 . The EEPROM semiconductor memory device according to  claim 6  wherein said word line and control gate drivers share decoder circuits. 
     
     
         9 . The EEPROM semiconductor memory device according to  claim 6  wherein said word line drivers and decoder circuits are separate from said control gate drivers and decoder circuits. 
     
     
         10 . The EEPROM semiconductor memory device according to  claim 6  wherein each of said control gate drivers and word line drivers is connected to a level shifter and wherein a control gate is selected by a select signal from said word line and control gate decoder via OR logic. 
     
     
         11 . The EEPROM semiconductor memory device according to  claim 6  wherein each of said control gate drivers is connected to a level shifter and wherein each four of said word line drivers are connected to one level shifter. 
     
     
         12 . The EEPROM semiconductor memory device according to  claim 6  wherein a control gate is selected by a signal from said word line and control gate decoder via OR logic and wherein a word line is selected by a signal from said word line and control gate decoder and a distributed power line. 
     
     
         13 . The EEPROM semiconductor memory device according to  claim 6  having a word line and control gate decoder and driver configuration for “CG shared driving” wherein each of said control gate drivers and word line drivers is connected to a level shifter and wherein a control gate is selected by a select signal from said word line and control gate decoder. 
     
     
         14 . The EEPROM semiconductor memory device having said CG shared driving configuration according to  claim 13  wherein one control gate driver is connected to every other two or more control gates. 
     
     
         15 . The EEPROM semiconductor memory device according to  claim 6  having a word line and control gate decoder and driver configuration for “CG shared driving” wherein each control gate driver is connected to a level shifter and wherein four word line drivers are connected to one level shifter. 
     
     
         16 . The EEPROM semiconductor memory device according to  claim 14  wherein a control gate is selected by a signal from said word line and control gate decoder and a word line is selected by a signal from said word line and control gate decoder and from distributed power lines. 
     
     
         17 . The EEPROM semiconductor memory device having said CG shared driving configuration according to  claim 15  wherein one control gate driver is connected to every other control gate. 
     
     
         18 . The EEPROM semiconductor memory device according to  claim 6  wherein each of said word line drivers comprises:
 an input signal; 
 an input voltage to be applied to a word line; and 
 an output word line with said applied voltage wherein said voltage is positive or negative. 
 
     
     
         19 . The EEPROM semiconductor memory device according to  claim 18  wherein a voltage condition for stand-by mode of said word line driver is:
 all word lines have a voltage applied of 0V. 
 
     
     
         20 . The EEPROM semiconductor memory device according to  claim 18  wherein a voltage condition for read mode of said word line driver is:
 a selected word line has a positive voltage applied; and 
 all unselected word lines have a voltage applied of 0V. 
 
     
     
         21 . The EEPROM semiconductor memory device according to  claim 18  wherein a voltage condition for program mode of said word line driver is:
 a selected word line has a positive voltage applied; and 
 all unselected word lines have a voltage applied of 0V. 
 
     
     
         22 . The EEPROM semiconductor memory device according to  claim 18  wherein a voltage condition for erase mode of said word line driver is:
 a selected word line has a negative voltage applied; and 
 all unselected word lines have a positive voltage applied. 
 
     
     
         23 . The EEPROM semiconductor memory device according to  claim 6  wherein each of said control gate drivers comprises:
 an input signal; 
 an input voltage to be applied to a control gate; and 
 an output control gate with said applied voltage wherein said voltage is positive or negative. 
 
     
     
         24 . The EEPROM semiconductor memory device according to  claim 23  wherein a voltage condition for stand-by mode of said control gate driver is:
 all control gates have a positive voltage applied. 
 
     
     
         25 . The EEPROM semiconductor memory device according to  claim 23  wherein a voltage condition for read mode of said control gate driver is:
 a selected control gate at the read side has a positive voltage applied; 
 a selected control gate at the override side has a positive voltage applied; and 
 all unselected control gates have a positive voltage applied. 
 
     
     
         26 . The EEPROM semiconductor memory device according to  claim 23  wherein a voltage condition for program mode of said control gate driver is:
 a selected control gate at the read side has a positive voltage applied; 
 a selected control gate at the override side has a positive voltage applied; and 
 all unselected control gates have a positive voltage applied. 
 
     
     
         27 . The EEPROM semiconductor memory device according to  claim 23  wherein a voltage condition for erase mode of said control gate driver is:
 a selected control gate at the erase side has a negative voltage applied; 
 a selected control gate at the override side has a positive voltage applied; and 
 all unselected control gates have a positive voltage applied. 
 
     
     
         28 . The EEPROM semiconductor memory device according to  claim 6  wherein said bit line decoder comprises:
 a number of input signals to select a number of adjacent bit lines; and 
 a voltage switch circuit to supply voltage to selected said bit lines. 
 
     
     
         29 . The EEPROM semiconductor memory device according to  claim 6  wherein said bit line controller comprises:
 a sense amplifier; 
 a precharge transistor; 
 a first and a second bit line bias voltage control transistors; 
 a verify and inhibit circuit; and 
 a reference decoder connected to a dummy memory cell. 
 
     
     
         30 . The EEPROM semiconductor memory device according to  claim 29  wherein said verify and inhibit circuit comprises:
 a data latch to hold read and program data from said sense amplifier and an external device, respectively; 
 a verify circuit comprising low voltage NMOS transistors and a VR node shared with other verify circuits of said bit line controller circuit and connected to said chip controller by a wired-OR circuit; and 
 a program inhibit circuit outputting a program inhibit voltage depending on the state of said data stored at said data latch during program operation. 
 
     
     
         31 . The EEPROM semiconductor memory device according to  claim 30  wherein:
 if a selected memory cell is programmed, said program inhibit circuit outputs a power supply voltage as a program inhibit voltage to the bit line of said selected memory cell at the override side; and 
 if a selected memory cell is not programmed, said program inhibit circuit outputs a ground voltage to the bit line of said selected memory cell at the override side. 
 
     
     
         32 . The EEPROM semiconductor memory device according to  claim 6  wherein a read operation procedure comprises:
 precharging a selected bit line to a positive voltage; 
 turning on selected control gates and word line; 
 applying a positive voltage to a selected control gate at the read side; 
 applying a positive voltage to a selected control gate at the override side; and 
 applying a positive voltage to said selected word line to read said selected memory cell. 
 
     
     
         33 . The EEPROM semiconductor memory device according to  claim 6  wherein an erase operation procedure comprises:
 applying a negative voltage to a selected control gate at the read side; 
 applying a positive voltage to an unselected control gate at the override side; 
 applying a negative voltage to a selected word line; 
 applying a positive voltage to an unselected WL; 
 applying a positive voltage to a selected bit line; and 
 applying a voltage of 0V to an unselected bit line to erase a selected memory cell. 
 
     
     
         34 . The EEPROM semiconductor memory device according to  claim 30  wherein a program and program verify operation procedure comprises:
 interleaving program and verify operation cycles wherein said program operation cycle comprises: 
 transmitting data from said external device to said data latch; 
 for each cell to be programmed:
 applying a positive voltage to a selected bit line at the program side; 
 applying a ground voltage to said selected bit line at the override side; 
 applying a positive voltage to a selected control gate at the selected cell side; 
 applying a positive voltage to said selected control gate at the override side; and 
 applying a positive voltage to the selected word line to write data ‘0’ to said memory cell; 
 
 for each memory cell not to be programmed:
 applying a positive voltage to selected bit lines at the program side; 
 applying a positive voltage to said selected bit lines at the override side; 
 applying a positive voltage to a selected control gate at the selected cell side; 
 applying a positive voltage to a selected control gate at the override side; and 
 applying a positive voltage to a selected word line whereby program is inhibited to write data “1” to said memory cell; 
 
 and wherein said verify operation comprises:
 after applying a program voltage to said selected memory cell, setting bias in a specified voltage to control the voltage for said selected bit line and said dummy memory cell; and 
 inhibiting said program operation for said selected memory cell to which said data “1” is written; 
 
 
       wherein said cycle of program & verify operation continues until all said memory cells which are to be programmed (writing the data “0”) are detected as “programmed”.