Twin MONOS Array for High Speed Application

Abstract

A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

What is claimed is: 
     
         1 . An erase inhibit procedure for a memory cell comprising:
 applying a negative voltage to a selected word line;   applying a positive voltage to all unselected word lines;   applying a negative voltage to a selected control gate at the erase side;   applying a positive voltage to a selected control gate at the override side;   applying a positive voltage to all unselected control gates;   applying a positive voltage to the selected bit line at the erase side; and   applying a positive voltage to the selected bit line at the override side wherein erase is inhibited in unselected cells and wherein only the selected memory cell is erased.   
     
     
         2 . A block erase procedure for a memory cell comprising:
 applying a negative voltage to all word lines in a selected block;   applying a negative voltage to all control gates in said selected block;   applying a positive voltage to all bit lines in said selected block; and   applying a zero voltage to all word lines, control gates, and bit lines in an unselected block wherein all cells within said selected block are erased.