Communicating a message request transaction to a logical device

Abstract

A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes logic to generate a signal that relates to a transaction involving a memory and includes a type field, an address field, and at least one field to indicate that another field of the signal is to include information.

What is claimed is: 
     
         1 . An apparatus comprising:
 a transmitter to:
 send a signal to another device over a channel of an interconnect comprising one or more point-to-point links, wherein the signal relates to a transaction involving a memory and includes a type field, an address field, and at least one field to indicate that another field of the signal is to include information. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the interconnect comprises a multi-layer interconnect. 
     
     
         3 . The apparatus of  claim 1 , wherein the signal further includes a transaction identifier. 
     
     
         4 . The apparatus of  claim 3 , wherein the transaction identifier includes at least four bits. 
     
     
         5 . The apparatus of  claim 3 , wherein the transaction identifier is to be unique among a set of transactions that await completion at the time of the transaction. 
     
     
         6 . The apparatus of  claim 1 , wherein another field of the signal includes an indication of whether a completion is to be sent for the transaction. 
     
     
         7 . The apparatus of  claim 1 , wherein the field indicating a format of information in the signal indicates data to be provided in one or more other fields of the signal. 
     
     
         8 . The apparatus of  claim 7 , wherein the transaction comprises a write transaction. 
     
     
         9 . The apparatus of  claim 7 , wherein the transaction comprises a read transaction. 
     
     
         10 . The apparatus of  claim 1 , wherein the type field is to comprise at least three bits. 
     
     
         11 . An apparatus comprising:
 a receiver to:
 receive a signal from another device, wherein the signal is to be received over one or more channels of an interconnect comprising one or more point-to-point links; and 
 interpret the signal, wherein the signal relates to a transaction involving a memory and includes a type field, an address field, and at least one field to indicate that another field of the signal is to include information. 
   
     
     
         12 . The apparatus of  claim 11 , wherein the interconnect comprises a multi-layer interconnect. 
     
     
         13 . The apparatus of  claim 11 , wherein the signal further includes a transaction identifier. 
     
     
         14 . The apparatus of  claim 13 , wherein the transaction identifier includes at least four bits. 
     
     
         15 . The apparatus of  claim 13 , wherein the transaction identifier is to be unique among a set of transactions that await completion at the time of the transaction. 
     
     
         16 . The apparatus of  claim 11 , wherein another field of the signal includes an indication of whether a completion is to be sent for the transaction. 
     
     
         17 . The apparatus of  claim 11 , wherein the field indicating a format of information in the signal indicates data to be provided in one or more other fields of the signal. 
     
     
         18 . The apparatus of  claim 11 , wherein the transaction comprises a write transaction. 
     
     
         19 . The apparatus of  claim 11 , wherein the transaction comprises a read transaction. 
     
     
         20 . The apparatus of  claim 11 , wherein the type field is to comprise at least three bits. 
     
     
         21 . An apparatus comprising:
 an I/O module to:
 receive a signal from another device, wherein the signal is received over one or more channels of a multilayer interconnect comprising one or more point-to-point links; and 
 interpret the signal, wherein the signal is to relate to a transaction involving a memory and is to include a type field, an address field, at least one field to indicate that another field of the signal is to include information, and another field to indicate whether a completion is to be sent for transaction, the type field is to be encoded according to a predefined set of type field encodings, and the transaction comprises a read transaction. 
   
     
     
         22 . A method comprising:
 sending a signal to another device over a channel of an interconnect comprising one or more point-to-point links, wherein the signal relates to a transaction involving a memory and includes a type field, an address field, and at least one field indicating a format of information in the signal; and   receiving a complete for the transaction from the other device.   
     
     
         23 . The method of  claim 22 , wherein the transaction comprises a write transaction. 
     
     
         24 . The method of  claim 22 , wherein the transaction comprises a read transaction. 
     
     
         25 . The method of  claim 22 , wherein the signal further includes a transaction identifier. 
     
     
         26 . The method of  claim 22 , wherein the message field further includes an indication of whether a completion is to be sent for an implemented message request transaction and the completion is received based on the indication. 
     
     
         27 . A system comprising:
 a first device;   a second device communicatively coupled to the first device using an interconnect fabric, wherein the second device comprises I/O logic to:
 send a signal to another device over a channel of an interconnect comprising one or more point-to-point links, wherein the signal relates to a transaction involving a memory and includes a type field, an address field, and at least one field indicating a format of information in the signal. 
   
     
     
         28 . The system of  claim 27 , wherein the first device comprises I/O logic to:
 receive a signal from another device, wherein the signal is received over one or more channels of an interconnect comprising one or more point-to-point links; and   interpret the signal, wherein the signal relates to a transaction involving a memory and includes a type field, an address field, and at least one field indicating a format of information in the signal.   
     
     
         29 . The system of  claim 27 , wherein the first device comprises a memory controller. 
     
     
         30 . The system of  claim 27 , wherein at least one of the first and second devices comprises a processor.