Method for fabricating dual damascene profiles using sub pixel-voting lithography and devices made by same

Abstract

This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure.

We claim: 
     
         1 . A method for processing a substrate, said method comprising the steps of:
 providing a single layer of radiation sensitive material on at least a portion of said substrate;   exposing a first area of said single layer of radiation sensitive material to radiation having a first intensity, wherein said first intensity is a sub-threshold level of intensity;   exposing a second area of said single layer of radiation sensitive material to radiation having a second intensity; wherein said second area at least partially overlaps said first area in an overlapping area and wherein said second intensity is a sub-threshold level of intensity; wherein said steps of exposing said first area and said second area of said single layer of radiation sensitive material to radiation having said first and second intensities are performed using maskless lithography;   developing said single layer of radiation sensitive material by removing material from regions of said single layer of radiation sensitive material corresponding to the first and second areas, thereby generating a recessed feature having a first non-uniform depth profile in said single layer of radiation sensitive material;   transferring at least a portion of said recessed feature having said first non-uniform depth profile in said single layer of radiation sensitive material into said substrate;   said transferring step generating a recessed feature having a second non-uniform depth profile in said substrate; and   depositing material onto said recessed feature having said second non-uniform depth profile to generate a structure at least partially embedded in said substrate, thereby processing said substrate.   
     
     
         2 . The method of  claim 1  wherein said recessed feature having said second non-uniform depth profile is an integrated trench and via structure in said substrate. 
     
     
         3 . The method of  claim 1  wherein said recessed feature having said second non-uniform depth profile is a Dual Damascene profile in said substrate. 
     
     
         4 . The method of  claim 1  wherein said overlapping area is exposed to a cumulative intensity of radiation equal to a sum of said first and second intensities. 
     
     
         5 . The method of  claim 4  wherein said cumulative intensity is between 2 and 10 times larger than said first intensity or said second intensity. 
     
     
         6 . The method of  claim 1  wherein said first and second intensities are large enough such that said overlapping area is exposed to a cumulative intensity of radiation large enough to provide complete removal of radiation sensitive material along an entire thickness of said single layer of radiation sensitive material corresponding to said overlapping area upon said developing step, thereby opening up a portion of said substrate corresponding to said overlapping area. 
     
     
         7 . The method of  claim 1  wherein portions of said first area and second area do not overlap in a non-overlapping area; wherein said first intensity and said second intensity are low enough such that said non-overlapping area is exposed to intensities of radiation that provide only partial removal upon said developing step of radiation sensitive material along a thickness of said single layer of radiation sensitive material corresponding to said non-overlapping area. 
     
     
         8 . The method of  claim 1  wherein said first area is selected from the range of 100 nanometers 2  to 500 microns 2 , wherein said second area is selected from the range of 100 nanometers 2  to 500 microns 2 , and wherein said overlapping area is selected from the range of 100 nanometers 2  to 100 microns 2 . 
     
     
         9 . The method of  claim 1  wherein said transferring step comprises removing material from said single layer of radiation sensitive material and removing material from said substrate. 
     
     
         10 . The method of  claim 9  wherein said transferring step comprises anisotropically etching said single layer of radiation sensitive material and said substrate. 
     
     
         11 . The method of  claim 9  wherein said transferring step comprises the step of simultaneously removing material from said single layer of radiation sensitive material and said substrate. 
     
     
         12 . The method of  claim 9  wherein said transferring step is independently carried out using a technique selected from the group consisting of reactive ion etching, wet etching, dry etching, photoablation, ion milling, reactive ion beam etching (RIBE), chemically assisted reactive ion beam etching (CAIBE), and plasma etching (PE). 
     
     
         13 . The method of  claim 1  further comprising the step of removing said single layer of radiation sensitive material after said transferring step. 
     
     
         14 . The method of  claim 1  further comprising the step of exposing one or more additional areas of said single layer of radiation sensitive material to radiation having a selected intensity; wherein said one or more additional areas of said single layer of radiation sensitive material overlap said first area, said second area or both of said first and second areas; wherein said first non-uniform depth profile of said recessed feature in said single layer of radiation sensitive material is a multi-step depth profile; and wherein said second non-uniform depth profile of said recessed feature in said substrate is a multi-step depth profile. 
     
     
         15 . The method of  claim 1  comprising a method of making a device selected from the group consisting of a transistor or array thereof, memory device, sensor, diode or array thereof, liquid crystal device, display device, optical source, microprocessor, a microfluidic system, a nanofluidic system, a nanoelectromechanical system, a microelectromechanical system, a wave guide, an optical system, an electro-optical system, an integrated circuit and interconnect structure. 
     
     
         16 . The method of  claim 1  wherein said depositing step is carried out using a technique selected from the group consisting of: physical vapor deposition, chemical vapor deposition, ion beam sputtering deposition, plasma enhanced chemical thin film deposition, electron beam evaporation deposition, atomic layer deposition, and thermal evaporation deposition. 
     
     
         17 . An electronic device or device component made by a method comprising the steps of:
 providing a single layer of radiation sensitive material on at least a portion of said substrate;   exposing a first area of said single layer of radiation sensitive material to radiation having a first intensity;   exposing a second area of said single layer of radiation sensitive material to radiation having a second intensity; wherein said second area of said layer at least partially overlaps said first area in an overlapping area, wherein said steps of exposing said first area and said second area of said single layer of radiation sensitive material are performed using maskless lithography;   developing said single layer of radiation sensitive material by removing material from regions of the layer corresponding to the first and second areas, thereby generating a recessed feature having a first non-uniform depth profile in said single layer of radiation sensitive material;   transferring at least a portion of said recessed feature having said first non-uniform depth profile in said single layer of radiation sensitive material into said substrate; said transferring step generating a recessed feature having a second non-uniform depth profile in said substrate; and   depositing material onto said recessed feature having said second non-uniform depth profile to generate a structure at least partially embedded in said substrate, thereby generating said electronic device or device component.   
     
     
         18 . The electronic device or device component of  claim 17 , comprising an electrical interconnect structure or a component of a device selected from the group consisting of a transistor or array thereof, a memory device, a sensor, a diode or array thereof, a liquid crystal device, a display device, an optical source, a microprocessor, a microfluidic system, a nanofluidic system, a nanoelectromechanical system, a microelectromechanical system, a wave guide, an optical system, an electro-optical system, and an integrated electronic circuit. 
     
     
         19 . The electronic device or device component of  claim 17 , wherein said second non-uniform depth profile comprises a via having a depth selected from the range of 300 nm to 400 nm and a trench having a depth selected from the range of 100 nm to 200 nm. 
     
     
         20 . An electronic device component comprising:
 a substrate layer stack, said substrate layer stack comprising a device layer, a first etch stop layer positioned over at least a portion of said device layer, a first substrate layer positioned over at least a portion of said first etch stop layer, a second etch stop layer positioned over at least a portion of said first substrate layer, a second substrate layer positioned over at least a portion of said second etch stop layer; wherein said substrate layer stack includes a recessed feature having a non-uniform depth profile, said recessed feature comprising a first absent portion of said first etch stop layer, a second absent portion of said first substrate layer, a third absent portion of said second etch stop layer and a fourth absent portion of said second substrate layer; and   a structure at least partially embedded in said recessed feature, said structure positioned in physical contact or electronic communication with at least a portion of said device layer.