Method and Apparatus for Generating Random Numbers

Abstract

A method for generating a random number with n RND bits BR i includes providing, in a memory, a static bit table (BFT) with m BFT addressable bits BT j , where 0≦j≦m BFT −1. The static bit table contains an equal number of “0” bits and “1” bits in a random distribution. In addition, for a bit BR i of said random number with 1≦i≦n RND , the method further includes generating, by a processor, an address FA in the range between 0 and m BFT −1, selecting, by the processor, the bit BT FA having the address FA from said static bit table, and setting, by the processor, said bit BR i of said random number to equal said bit BT FA from said static bit table (BR i =BT FA ).

What is claimed is: 
     
         1 . A method for generating a random number with n RND  bits BR i , wherein 1≦i≦n RND , said method comprising:
 a) providing, in a memory, a static bit table (BFT) with m BFT  addressable bits BT j , wherein 0≦j≦m BFT −1, said static bit table containing an equal number of “0” bits and “1” bits in a random distribution, and 
 b) for a bit BR i  of said random number with 1≦i≦n RND  
 i. generating, by a processor, an address FA in the range between 0 and m BFT −1, 
 ii. selecting, by the processor, the bit BT FA  having the address FA from said static bit table, and 
 iii. setting, by the processor, said bit BR i  of said random number to equal said bit BT FA  from said static bit table (BR i =BT FA ). 
 
 
     
     
         2 . The method according to  claim 1 , wherein generating an address FA comprises:
 c) providing a number q of basic randomness values BRV, each basic randomness value BRV having a length of l bits   d) extracting selected ones of the l bits of each of said q basic randomness values BRV and assembling said address FA from said selected bits.   
     
     
         3 . The method according to  claim 2 , wherein extracting selected ones of the l bits of said q basic randomness value BRV comprises executing an “AND”-operation of each of said q basic randomness value BRV and a selected one of a number of predetermined specific final address assembly parameters FAAP, and
 wherein assembling said address FA from said selected bits comprises transferring the results of said “AND”-operations into a final address register. 
 
     
     
         4 . The method according to  claim 3 , wherein said final address parameters FAAP are configured such that for each bit BR i  of the random number to be generated, the number p FA  of bits selected from each basic randomness value BRV for assembling said address FA is identical. 
     
     
         5 . The method according to  claim 4 , wherein said final address parameters FAAP are configured such that after the generation of 
       
         
           
             
               l 
               
                 p 
                 FA 
               
             
           
         
       
       bits BR i  of the random number, each one of said l bits of a basic randomness value BRV has been selected exactly once. 
     
     
         6 . The method according to  claim 2 , wherein said basic randomness values BRV are generated by
 e) generating a pseudo-random number PRND;   f) providing at least one feedback modifier value FBM, said feedback modifier being influenced by a predetermined number of previously generated bits BR i , and   g) executing an XOR-operation of at least a part of said generated pseudo-random number with said at least one feedback modifier value FBM.   
     
     
         7 . The method according to  claim 6 , wherein the pseudo-random number PRND generated in step e) has a length of l PRND  bits and is generated by a linear congruential generator, l PRND ≧l,
 wherein said at least one feedback modifier value FBM provided in step f) has a length of l bits, and 
 wherein the at least a part of said generated pseudo-random number used in the XOR-operation of step g) are the last l bits of said generated pseudo-random number PRND. 
 
     
     
         8 . The method according to  claim 6 , wherein said at least one feedback modifier value FBM is generated by executing an XOR-operation of a predetermined l-bit long basic modifier value BM with the last l previously generated bits BR i . 
     
     
         9 . The method according to  claim 6 , wherein said at least one feedback modifier value FBM is periodically renewed. 
     
     
         10 . The method according to  claim 8 , wherein said at least one feedback modifier value FBM is generated by executing an XOR-operation of one of a plurality of predetermined l-bit long basic modifier values BM with the last l previously generated bits BR i , and wherein after each generation of a feedback modifier, the basic modifier values BM of said plurality of basic modifier values BM are cyclically permuted. 
     
     
         11 . The method according to  claim 8 , wherein said basic modifier value BM is generated during an initialization step of the method by alternatively filling blocks of two values, one block with the result of an XOR-operation of a generated pseudo-random number with randomly selected bits of said static bit table (BFT) and one block with an unmodified generated pseudo-random number. 
     
     
         12 . A computer device comprising:
 a memory having program code stored therein for performing a method; and   an execution environment including a processor for executing said program code so as to carry out said method, the method comprising:   a) providing, in a memory, a static bit table (BFT) with m BFT  addressable bits BT j , wherein 0≦j≦m BFT −1, said static bit table containing an equal number of “0” bits and “1” bits in a random distribution, and   b) for a bit BR i  of said random number with 1≦i≦n RND  
 i. generating, by a processor, an address FA in the range between 0 and m BFT −1, 
 ii. selecting, by the processor, the bit BT FA  having the address FA from said static bit table, and 
 iii. setting, by the processor, said bit BR i  of said random number to equal said bit BT FA  from said static bit table (BR i =BT FA ). 
   
     
     
         13 . A computer device according to  claim 12 , further comprising amending, by the processor, one or more initial parameters for said method at each power-up. 
     
     
         14 . The computer device according to  claim 12 , wherein generating an address FA comprises:
 c) providing a number q of basic randomness values BRV, each basic randomness value BRV having a length of l bits, and   d) extracting selected ones of the l bits of each of said q basic randomness values BRV and assembling said address FA from said selected bits.   
     
     
         15 . The computer device according to  claim 14 , wherein extracting selected ones of the l bits of said q basic randomness value BRV comprises executing an “AND”-operation of each of said q basic randomness value BRV and a selected one of a number of predetermined specific final address assembly parameters FAAP, and
 wherein assembling said address FA from said selected bits comprises transferring the results of said “AND”-operations into a final address register. 
 
     
     
         16 . The computer device according to  claim 15 , wherein said final address parameters FAAP are configured such that for each bit BR i  of the random number to be generated, the number p FA  of bits selected from each basic randomness value BRV for assembling said address FA is identical. 
     
     
         17 . The computer device according to  claim 16 , wherein said final address parameters FAAP are configured such that after the generation of 
       
         
           
             
               l 
               
                 p 
                 FA 
               
             
           
         
       
       bits BR i  of the random number, each one of said l bits of a basic randomness value BRV has been selected exactly once. 
     
     
         18 . The computer device according to  claim 14 , wherein said basic randomness values BRV are generated by:
 e) generating a pseudo-random number PRND;   f) providing at least one feedback modifier value FBM, said feedback modifier being influenced by a predetermined number of previously generated bits BR i , and   g) executing an XOR-operation of at least a part of said generated pseudo-random number with said at least one feedback modifier value FBM.   
     
     
         19 . The computer device according to  claim 18 , wherein the pseudo-random number PRND generated in step e) has a length of l PRND  bits and is generated by a linear congruential generator, l  PRND ≧l;
 wherein said at least one feedback modifier value FBM provided in step f) has a length of l bits, and 
 wherein the at least a part of said generated pseudo-random number used in the XOR-operation of step g) are the last l bits of said generated pseudo-random number PRND. 
 
     
     
         20 . The computer device according to  claim 18 , wherein said at least one feedback modifier value FBM is generated by executing an XOR-operation of a predetermined l-bit long basic modifier value BM with the last l previously generated bits BR i . 
     
     
         21 . The computer device according to  claim 20 , wherein said at least one feedback modifier value FBM is generated by executing an XOR-operation of one of a plurality of predetermined l-bit long basic modifier values BM with the last l previously generated bits BR i , and wherein after each generation of a feedback modifier, the basic modifier values BM of said plurality of basic modifier values BM are cyclically permuted. 
     
     
         22 . The computer device according to  claim 20 , wherein said basic modifier value BM is generated during an initialization step of the method by alternatively filling blocks of two values, one block with the result of an XOR-operation of a generated pseudo-random number with randomly selected bits of said static bit table (BFT) and one block with an unmodified generated pseudo-random number. 
     
     
         23 . The computer device according to  claim 18 , wherein said at least one feedback modifier value FBM is periodically renewed. 
     
     
         24 . A method for encrypting data by generating a random number with n RND  bits BR i , wherein 1≦i≦n RND , said method comprising:
 a) providing, in a memory, a static bit table (BFT) with m BFT  addressable bits BT j , wherein 0≦j≦m BFT −1, said static bit table containing an equal number of “0” bits and “1” bits in a random distribution; 
 b) for a bit BR i  of said random number with 1≦i≦n RND  
 i. generating, by a processor, an address FA in the range between 0 and m BFT −1, 
 ii. selecting, by the processor, the bit BT FA  having the address FA from said static bit table, and 
 iii. setting, by the processor, said bit BR i  of said random number to equal said bit BT FA  from said static bit table (BR i =BT FA ); and 
 
 c) encrypting said data with said random number. 
 
     
     
         25 . The method according to  claim 24 , wherein generating an address FA comprises:
 d) providing a number q of basic randomness values BRV, each basic randomness value BRV having a length of l bits   e) extracting selected ones of the l bits of each of said q basic randomness values BRV and assembling said address FA from said selected bits.   
     
     
         26 . The method according to  claim 25 , wherein extracting selected ones of the l bits of said q basic randomness value BRV comprises executing an “AND”-operation of each of said q basic randomness value BRV and a selected one of a number of predetermined specific final address assembly parameters FAAP, and
 wherein assembling said address FA from said selected bits comprises transferring the results of said “AND”-operations into a final address register. 
 
     
     
         27 . The method according to  claim 26 , wherein said final address parameters FAAP are configured such that for each bit BR i  of the random number to be generated, the number p FA  of bits selected from each basic randomness value BRV for assembling said address FA is identical. 
     
     
         28 . The method according to  claim 27 , wherein said final address parameters FAAP are configured such that after the generation of 
       
         
           
             
               l 
               
                 p 
                 FA 
               
             
           
         
       
       bits BR i  of the random number, each one of said l bits of a basic randomness value BRV has been selected exactly once. 
     
     
         29 . The method according to  claim 25 , wherein said basic randomness values BRV are generated by
 f) generating a pseudo-random number PRND;   g) providing at least one feedback modifier value FBM, said feedback modifier being influenced by a predetermined number of previously generated bits BR i , and   h) executing an XOR-operation of at least a part of said generated pseudo-random number with said at least one feedback modifier value FBM.   
     
     
         30 . The method according to  claim 29 , wherein the pseudo-random number PRND generated in step f) has a length of l PRND  bits and is generated by a linear congruential generator, l PRND ≧l,
 wherein said at least one feedback modifier value FBM provided in step g) has a length of l bits, and 
 wherein the at least a part of said generated pseudo-random number used in the XOR-operation of step h) are the last l bits of said generated pseudo-random number PRND. 
 
     
     
         31 . The method according to  claim 29 , wherein said at least one feedback modifier value FBM is generated by executing an XOR-operation of a predetermined l-bit long basic modifier value BM with the last l previously generated bits BR i . 
     
     
         32 . The method according to  claim 29 , wherein said at least one feedback modifier value FBM is periodically renewed. 
     
     
         33 . The method according to  claim 31 , wherein said at least one feedback modifier value FBM is generated by executing an XOR-operation of one of a plurality of predetermined l-bit long basic modifier values BM with the last l previously generated bits BR i , and wherein after each generation of a feedback modifier, the basic modifier values BM of said plurality of basic modifier values BM are cyclically permuted. 
     
     
         34 . The method according to  claim 31 , wherein said basic modifier value BM is generated during an initialization step of the method by alternatively filling blocks of two values, one block with the result of an XOR-operation of a generated pseudo-random number with randomly selected bits of said static bit table (BFT) and one block with an unmodified generated pseudo-random number. 
     
     
         35 . A computer device comprising:
 a memory having program code stored therein for performing a method; and   an execution environment including a processor for executing said program code so as to carry out said method, the method comprising:   a) providing, in a memory, a static bit table (BFT) with m BFT  addressable bits BT j , wherein 0≦j≦m BFT −1, said static bit table containing an equal number of “0” bits and “1” bits in a random distribution;   b) for a bit BR i  of said random number with 1≦i≦n RND  
 i. generating, by a processor, an address FA in the range between 0 and m BFT −1, 
 ii. selecting, by the processor, the bit BT FA  having the address FA from said static bit table, and 
 iii. setting, by the processor, said bit BR i  of said random number to equal said bit BT FA  from said static bit table (BR i =BT FA ); and 
   c) encrypting said data with said random number.   
     
     
         36 . A computer device according to  claim 35 , further comprising amending, by the processor, one or more initial parameters for said method at each power-up. 
     
     
         37 . The computer device according to  claim 35 , wherein generating an address FA comprises:
 d) providing a number q of basic randomness values BRV, each basic randomness value BRV having a length of l bits, and   e) extracting selected ones of the l bits of each of said q basic randomness values BRV and assembling said address FA from said selected bits.   
     
     
         38 . The computer device according to  claim 37 , wherein extracting selected ones of the l bits of said q basic randomness value BRV comprises executing an “AND”-operation of each of said q basic randomness value BRV and a selected one of a number of predetermined specific final address assembly parameters FAAP, and wherein assembling said address FA from said selected bits comprises transferring the results of said “AND”-operations into a final address register. 
     
     
         39 . The computer device according to  claim 38 , wherein said final address parameters FAAP are configured such that for each bit BR i  of the random number to be generated, the number p FA  of bits selected from each basic randomness value BRV for assembling said address FA is identical. 
     
     
         40 . The computer device according to  claim 39 , wherein said final address parameters FAAP are configured such that after the generation of 
       
         
           
             
               l 
               
                 p 
                 FA 
               
             
           
         
       
       bits BR i  of the random number, each one of said l bits of a basic randomness value BRV has been selected exactly once. 
     
     
         41 . The computer device according to  claim 37 , wherein said basic randomness values BRV are generated by:
 f) generating a pseudo-random number PRND;   g) providing at least one feedback modifier value FBM, said feedback modifier being influenced by a predetermined number of previously generated bits BR i , and   h) executing an XOR-operation of at least a part of said generated pseudo-random number with said at least one feedback modifier value FBM.   
     
     
         42 . The computer device according to  claim 41 , wherein the pseudo-random number PRND generated in step f) has a length of l PRND  bits and is generated by a linear congruential generator, l PRND ≧l;
 wherein said at least one feedback modifier value FBM provided in step g) has a length of l bits, and 
 wherein the at least a part of said generated pseudo-random number used in the XOR-operation of step h) are the last l bits of said generated pseudo-random number PRND. 
 
     
     
         43 . The computer device according to  claim 41 , wherein said at least one feedback modifier value FBM is generated by executing an XOR-operation of a predetermined l-bit long basic modifier value BM with the last l previously generated bits BR i . 
     
     
         44 . The computer device according to  claim 43 , wherein said at least one feedback modifier value FBM is generated by executing an XOR-operation of one of a plurality of predetermined l-bit long basic modifier values BM with the last l previously generated bits BR i , and wherein after each generation of a feedback modifier, the basic modifier values BM of said plurality of basic modifier values BM are cyclically permuted. 
     
     
         45 . The computer device according to  claim 43 , wherein said basic modifier value BM is generated during an initialization step of the method by alternatively filling blocks of two values, one block with the result of an XOR-operation of a generated pseudo-random number with randomly selected bits of said static bit table (BFT) and one block with an unmodified generated pseudo-random number. 
     
     
         46 . The computer device according to  claim 41 , wherein said at least one feedback modifier value FBM is periodically renewed.