Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a semiconductor substrate in which an active region and an isolation region are defined;   a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region;   a trench formed in the semiconductor substrate in the isolation region;   a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench; and   a control gate formed on the dielectric layer,   wherein the dielectric layer includes a first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the first nitride layer, the first oxide layer, the second nitride layer and the second oxide layer extend both in the active region and the isolation region. 
     
     
         3 . The semiconductor memory device of  claim 1 , further comprising a liner insulating layer formed along a surface of the trench in the isolation region. 
     
     
         4 . The semiconductor memory device of  claim 1 , further comprising a lower insulating layer formed under the air gap in the isolation region. 
     
     
         5 . The semiconductor memory device of  claim 4 , wherein a top surface of the lower insulating layer is lower than a top surface of the semiconductor substrate in the active region. 
     
     
         6 . A method of manufacturing a semiconductor memory device, the method comprising:
 forming a tunnel insulating layer and a first conductive layer configured as a floating gate in an active region of a semiconductor substrate, and forming a trench in an isolation region of the semiconductor substrate;   filling the trench with a sacrificial layer having a top surface higher than a surface of the semiconductor substrate;   forming a first oxide layer along an entire surface of a resultant structure filled with the sacrificial layer;   forming an air gap in the isolation region by removing the sacrificial layer while maintaining the first oxide layer;   transforming a portion of the first oxide layer into a first nitride layer;   forming a second nitride layer and a second oxide layer over the first oxide layer; and   forming a second conductive layer configured as a control gate on the second oxide layer.   
     
     
         7 . The method of  claim 6 , wherein the first oxide layer includes an ultra low temperature oxide layer. 
     
     
         8 . The method of  claim 6 , wherein the ultra low temperature oxide layer is formed using atomic layer deposition (ALD). 
     
     
         9 . The method of  claim 6 , wherein the ultra low temperature oxide layer is formed at a temperature ranging from approximately 50° C. to 100° C. 
     
     
         10 . The method of  claim 6 , wherein the first nitride layer is formed by transforming a lower portion of the first oxide layer into an SiON layer. 
     
     
         11 . The method of  claim 6 , wherein the first nitride layer is formed by performing plasma nitridation or annealing. 
     
     
         12 . The method of  claim 11 , wherein the plasma nitridation is performed under a nitrogen atmosphere at a temperature ranging from approximately 200° C. to 700° C. 
     
     
         13 . The method of  claim 11 , further comprising performing a stabilized process to improve quality of the first nitride layer after the first nitride layer is formed by performing the plasma nitridation. 
     
     
         14 . The method of  claim 13 , wherein the stabilizing process is performed by a plasma process under an oxygen atmosphere. 
     
     
         15 . The method of  claim 11 , wherein the annealing is performed at a temperature ranging from 600° C. to 1100° C. 
     
     
         16 . The method of  claim 11 , wherein the annealing is performed under an NO, N 2  or N 2 O atmosphere. 
     
     
         17 . The method of  claim 6 , further comprising performing additional oxidation to improve quality of the first oxide layer after the transforming of the portion of the first oxide layer into the first nitride layer. 
     
     
         18 . The method of  claim 17 , wherein O 2  dry oxidation or O 2  wet annealing is performed as the additional oxidation. 
     
     
         19 . The method of  claim 6 , further comprising forming a lower insulating layer in a lower part of the trench before the filling of the sacrificial layer. 
     
     
         20 . The method of  claim 6 , wherein the forming of the air gap in the isolation region is performed by generating oxygen, nitrogen or hydrogen plasma to remove the sacrificial layer.