US2014151784A1PendingUtilityA1
Semiconductor memory device and method of manufacturing the same
Est. expiryNov 30, 2032(~6.3 yrs left)· nominal 20-yr term from priority
Inventors:Sang Hyon Kwak
H10D 64/0111H10D 30/693H10D 30/63H10D 84/016H10D 30/025H10B 43/27H10W 10/014H10B 41/27H01L 29/66666H01L 29/7827
44
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Claims
Abstract
The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. A seed pattern is formed on a surface of the trench and a metal layer is formed on the seed pattern in the trench.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor memory device, comprising:
a channel layer; interlayer insulation layers surrounding the channel layer, wherein the interlayer insulation layers are stacked with a trench interposed therebetween; a seed pattern formed on a surface of the trench; and a metal layer formed on the seed pattern in the trench.
2 . The semiconductor memory device of claim 1 , wherein the metal layer covers an entire surface of the seed pattern.
3 . The semiconductor memory device of claim 1 , wherein a width of each of the interlayer insulation layers is greater than a width of the seed pattern.
4 . The semiconductor memory device of claim 1 , wherein a width of the metal layer is greater or less than a width of each of the interlayer insulation layers.
5 . The semiconductor memory device of claim 1 , further comprising:
barrier metal patterns formed between the seed pattern and the channel layer and between the seed pattern and the interlayer insulation layers.
6 . The semiconductor memory device of claim 1 , wherein the metal layer is formed of tungsten.
7 . A method of manufacturing a semiconductor memory device, the method comprising:
forming interlayer insulation layers surrounding a channel layer, wherein the interlayer insulation layers are stacked with a trench interposed therebetween; forming a seed film on a surface of the trench and on surfaces of the interlayer insulation layers; forming a sacrificial pattern in the trench; forming a seed pattern in the trench by etching the seed film by using the sacrificial pattern as an etching barrier; and growing a metal layer from the seed pattern in the trench.
8 . The method of claim 7 , wherein the forming of the interlayer insulation layers surrounding the channel layer comprises:
alternately stacking the interlayer insulation layers and sacrificial layers; forming the channel layer through the interlayer insulation layers and the sacrificial layers; forming a slit through the interlayer insulation layers and the sacrificial layers to expose the sacrificial layers; and forming the trench by removing the sacrificial layers.
9 . The method of claim 7 , further comprising:
forming a barrier metal layer along a surface of the trench and along surfaces of the interlayer insulation layers before the forming of the seed film.
10 . The method of claim 7 , further comprising:
forming a barrier metal pattern under the seed pattern by etching the barrier metal layer by using the sacrificial pattern as an etching barrier.
11 . The method of claim 7 wherein a width of the sacrificial pattern is less than a width of each of the interlayer insulation layers.
12 . The method of claim 7 , wherein the metal layer is to cover an entire surface of the seed pattern.
13 . The method of claim 7 , wherein a width of the metal layer is greater or less than a width of each of the interlayer insulation layers.
14 . The method of claim 7 , wherein the forming the seed film comprises:
forming the seed film using a reducing gas.
15 . The method of claim 14 , wherein the growing the metal layer comprises:
removing the reducing gas using a purge gas; and substituting the seed pattern with the metal layer via a metal source gas.Join the waitlist — get patent alerts
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