Partial poly amorphization for channeling prevention

Abstract

Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

What is claimed is: 
     
         1 . A device comprising:
 a substrate,   a gate formed on the substrate, the gate comprising a polycrystalline silicon layer formed in a lower two thirds of the gate; and   a source/drain region in the substrate on each side of the gate;   a first silicide formed in an upper one third of the gate; and   a second silicide on each source/drain region, wherein the first silicide has a thickness greater than the second silicide.   
     
     
         2 . The device according to  claim 1 , wherein the upper one third of the gate comprises amorphized silicon. 
     
     
         3 . The device according to  claim 1 , wherein a thickness of the polycrsytalline silicon layer is 300 Å to 500 Å. 
     
     
         4 . The device according to  claim 1 , wherein the thickness of the first silicide is 20% to 30% greater than the thickness of the second silicide. 
     
     
         5 . The device according to  claim 1 , further comprising halo/extension regions in the substrate on each side of the gate. 
     
     
         6 . The device according to  claim 1 , further comprising spacers on each side of the gate. 
     
     
         7 . The device according to  claim 1 , wherein the source/drain regions ions implanted in the substrate. 
     
     
         8 . The device according to  claim 1 , wherein the source/drain regions comprise. embedded silicon germanium (eSiGe) source/drain regions in the substrate. 
     
     
         9 . A device comprising:
 a substrate,   at least one gate formed on the substrate, the gate comprising a polycrystalline silicon layer having a thickness of 300 Å to 500 Å formed in a lower two thirds of each gate and an amorphized silicon layer formed in an upper one third of each gate; and   a source/drain region in the substrate on each side of each gate;   a first silicide formed in the amorphized silicon layer of each gate; and   a second silicide on each source/drain region, wherein the first silicide has a thickness greater than the second silicide.   
     
     
         10 . The device according to  claim 9 , comprising two gates wherein a source/drain region on each side of the first gate comprises embedded silicon germanium (eSiGe) source/drain regions in the substrate and a source/drain region on each side of the second gate comprises ions implanted in the substrate. 
     
     
         11 . The device according to  claim 9 , wherein the thickness of the first silicide is 20% to 30% greater than the thickness of the second silicide. 
     
     
         12 . The device according to  claim 9 , further comprising halo/extension regions in the substrate on each side of each gate. 
     
     
         13 . The device according to  claim 9 , further comprising spacers on both sides of each gate. 
     
     
         14 . A device comprising:
 a substrate,   an n-type and a p-type gate formed on the substrate, each gate comprising a polycrystalline silicon layer formed in a lower two thirds of the gate;   a shallow trench isolation (STI) region formed in the substrate between the n-type and the p-type gates; and   an embedded silicon germanium (eSiGe) source/drain region in the substrate on each side of the p-type gate;   an ion implanted source/drain region in the substrate on each side of the n-type gate;   a first silicide formed in an upper one third of each of the p-type and n-type gates; and   a second silicide on each eSiGe and each ion implanted source/drain region, wherein the first silicide has a thickness greater than the second silicide.   
     
     
         15 . The device according to  claim 14 , wherein the upper one third of each of the p-type and n-type gates comprises amorphized silicon. 
     
     
         16 . The device according to  claim 14 , wherein a thickness of the polycrsytalline silicon layer is 300 Å to 500 Å. 
     
     
         17 . The device according to  claim 14 , wherein the thickness of the first silicide is 20% to 30% greater than the thickness of the second silicide. 
     
     
         18 . The device according to  claim 14 , wherein the ion implanted source/drain regions comprise arsenic (As) or boron (B) ions implanted in the substrate. 
     
     
         19 . The device according to  claim 14 , further comprising halo/extension regions in the substrate on each side of each of the p-type and n-type gates. 
     
     
         20 . The device according to  claim 14 , further comprising spacers on both sides of each of the p-type and n-type gates.