Method and System for Multiple I/O Regions

Abstract

Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available standard I/O libraries in conjunction with standard IC design flows and tools and in combination with one or more novel standardized I/O region interconnect cells for interconnecting between or through otherwise separated I/O regions. Specific embodiments support a wide variety of IC's that can be developed using standard libraries and design flows including: application specific integrated circuits (ASIC's), programmable logic devices (PLDs), custom IC's, analog IC's, CPU's, GPU's, and other IC's that require large numbers of input/ouput (IO) circuits while having relatively small core circuitry areas. Specific embodiments may involve innovative I/O cell functions, innovative IC topologies, and innovative IC packaging solutions for single die packages and multiple die packages.

1 . A method for creating an integrated circuit (IC) design that includes multiple I/O regions said I/O regions comprising at least one outer I/O region and one inner I/O region, comprising:
 providing a plurality of interconnect cells, said interconnect cells providing at least one lateral signal path for laterally connecting signals in an I/O region, said interconnect cells also providing at least one interconnect signal path for connecting signals between or through I/O regions;   providing a set of I/O cells;   placing I/O cells into at least one outer I/O region and one inner I/O region; and   placing at least one interconnect cell in at least one inner I/O region.   
     
     
         2 . The method of  claim 1  further comprising:
 providing one or more software design tools for placing said I/O cells and said interconnect cells. 
 
     
     
         3 . The method of  claim 1  further comprising:
 the set of I/O cells being of a type that includes filler cells with lateral connections between abutting I/O cells; and 
 providing one or more interconnect cells that have a width of a filler cell of the set of I/O cells. 
 
     
     
         4 . The method of  claim 3  further comprising:
 providing one or more interconnect cells of an “L” or “T” shape and that have a vertical width of a filler cell of the set of I/O cells. 
 
     
     
         5 . The method of  claim 1  further comprising:
 the set of I/O cells being of a type that includes filler cells with lateral connections between abutting I/O cells; and 
 providing one or more interconnect cells, the interconnect cells comprising: 
 at least one flow-through filler portion having a width roughly equal to the width of a filler cell and containing lateral and transverse connections; 
 at least one inter-region portion that lies between outer I/O region cells and inner I/O region cells and that routes signals from the edge of an inner I/O region around to transverse connections in a flow-through filler portion. 
 
     
     
         6 . The method of  claim 5  further wherein:
 flow-through filler portions and inter-region portions can be separately placed cells and can also be grouped into “L” or “T” cells of various capacities. 
 
     
     
         7 . The method of  claim 1  further comprising:
 providing one or more interconnect cells, the interconnect cells large enough to contain I/O cells and also comprising: 
 at least one flow-through filler portion containing lateral and transverse connections; 
 at least one inter-region portion that lies between an outer I/O region and an inner I/O region and that routes signals from the edge of an inner I/O region around to transverse connections in a flow-through filler portion. 
 
     
     
         8 . The method of  claim 1  further comprising:
 placing an inner I/O cell inside an interconnect cell. 
 
     
     
         9 . The method of  claim 1  further comprising:
 providing one or more interconnect cells selected from the group: 
 input interconnect cells; 
 output interconnect cells; 
 tri-state interconnect cells; 
 bidirectional interconnect cells; 
 dynamically configurable interconnect cells; 
 high capacity interconnect cells; 
 corner feed-through interconnect cells; 
 power interconnect cells; 
 power supply interconnect cells; 
 I/O ring inter-connection I/O cells; 
 T-connection interconnect cells; 
 3 way-corner interconnect cells. 
 
     
     
         10 . The method of  claim 1  further comprising:
 providing one or more interconnect cells selected from the group: 
 flow-through cells; 
 I/O region connector cells. 
 
     
     
         11 . The method of  claim 1  further comprising:
 providing one or more interconnect cells comprising at least one lateral signal path and at least one transverse power signal path for connecting power lateral signals between an inner I/O region and an outer I/O region. 
 
     
     
         12 . The method of  claim 2  further comprising:
 using said software design tool to place I/O cells into at least two I/O regions comprising an outer I/O region and an inner I/O region; 
 wherein said two I/O regions provide a compound I/O structure selected from the group:
 a compound I/O structure having two concentric JO rings; 
 a compound I/O structure having three or more concentric I/O rings; 
 a compound I/O structure having an outer I/O ring surrounding two inner I/O rings that surround two core areas; 
 a compound I/O structure having an outer I/O ring surrounding a separate core area plus two inner I/O rings that surround two core areas; 
 a compound I/O structure having an outer I/O ring that surrounds a separate core area plus an inner I/O ring surrounding another core area; 
 a compound I/O structure having additional I/O Stripes along sides; 
 a compound I/O structure having I/O stripes in the core area; 
 a compound I/O structure having interconnected partial I/O ring in the core area; and 
 a compound I/O structure providing an IC partitioned to have multiple core areas for supply isolation, analog circuitry isolation, and high-speed signal isolation etc. 
 
 
     
     
         13 . The method of  claim 2  further comprising:
 using said software design tool to place I/O cells into at least two I/O regions comprising an outer I/O region and an inner I/O region; and 
 connecting one or more I/O cells in said inner I/O region to bond-pads of a chip-on-chip sub-chip. 
 
     
     
         14 . (canceled) 
     
     
         15 . The method of  claim 1  further comprising:
 grouping one or more interconnect cells and one or more I/O cells into a rectangular unit for placement by software design tools. 
 
     
     
         16 . The method of  claim 1  further comprising:
 aligning I/O cells in the inner and outer I/O regions with filler cells and interconnect cells as needed. 
 
     
     
         17 . The method of  claim 1  further wherein:
 a majority of inner region I/O cells and outer region I/O cells are selected from a common set of cells, with the interconnect cells providing necessary spacing and interconnections to allow a common set of I/O cells to be used in inner and outer I/O regions. 
 
     
     
         18 . The method of  claim 1  further wherein:
 a majority of inner region I/O cells and outer region I/O cells are selected from a common set of I/O cells designed for simple I/O structures without modifications to allow them to be used in compound I/O region designs. 
 
     
     
         19 . (canceled) 
     
     
         20 . A semiconductor integrated circuit of a type constructed using a set of repeated I/O cells in an I/O region and at least one core area, wherein a portion of the I/O region comprises multiple laterally abutting I/O cells, the integrated circuit being of a type having an outer I/O region, the semiconductor integrated circuit comprising:
 at least one additional I/O region comprising abutting I/O cells with lateral connections; and   at least one of the repeated I/O cells configured to pass I/O signals through the additional I/O region while also making lateral connections in the additional I/O region.   
     
     
         21 . The semiconductor integrated circuit of  claim 20  further comprising:
 at least one of said I/O cells being one or more selected from the group: 
 input interconnect cells; 
 output interconnect cells; 
 tri-state interconnect cells; 
 bidirectional interconnect cells; 
 dynamically configurable interconnect cells; 
 high capacity interconnect cells; 
 corner feed through interconnect cells; 
 power interconnect cells; 
 power supply interconnect cells; 
 I/O ring inter-connection I/O cells; 
 T-connection interconnect cells; and 
 3 way-corner interconnect cells. 
 
     
     
         22 . (canceled) 
     
     
         23 . The semiconductor integrated circuit of  claim 20  further wherein:
 the inner I/O region is an I/O ring substantially surrounding at least a portion of the core. 
 
     
     
         24 . The semiconductor integrated circuit of  claim 20  further wherein:
 the inner I/O region is an I/O stripe, receiving at least one signal from an interconnect cell. 
 
     
     
         25 . The semiconductor integrated circuit of  claim 20  further wherein:
 the outer I/O region is one or more I/O stripes. 
 
     
     
         26 . The semiconductor integrated circuit of  claim 20  further wherein:
 the inner I/O region is an I/O ring substantially surrounding at least a portion of said core. 
 
     
     
         27 . The semiconductor integrated circuit of  claim 20  further wherein:
 the inner I/O region is an I/O stripe, receiving at least one signal from an interconnect cell. 
 
     
     
         28 . The semiconductor integrated circuit of  claim 20  further wherein:
 the inner I/O region provides I/O connections to one or more CoC (Chip on Chip) chips. 
 
     
     
         29 . The semiconductor integrated circuit of  claim 20  further wherein:
 the IC has I/O regions provide a compound I/O structure selected from the group:
 a compound I/O structure having two concentric IO rings; 
 a compound I/O structure having three or more concentric I/O rings; 
 a compound I/O structure having an outer I/O ring surrounding two inner I/O rings that surround two core areas; 
 a compound I/O structure having an outer I/O ring surrounding a separate core area plus two inner I/O rings that surround two core areas; 
 a compound I/O structure having an outer I/O ring that surrounds a separate core area plus an inner I/O ring surrounding another core area; 
 a compound I/O structure having additional I/O Stripes along sides; 
 a compound I/O structure having I/O stripes in the core area; 
 a compound I/O structure having interconnected partial I/O ring in the core area; and 
 a compound I/O structure providing an IC partitioned to have multiple core areas for supply isolation, analog circuitry isolation, and high-speed signal isolation etc. 
 
 
     
     
         30 . The semiconductor integrated circuit of  claim 20  further wherein:
 a plurality of the I/O cells provide lateral I/O cell connections to efficiently distribute I/O and core power and ground supplies to the I/O cells and thus minimize I/O signal noise and maximize electrostatic discharge (ESD) protection; 
 a plurality of the I/O cells contain interface circuitry for higher supply voltage external signals and for lower supply voltage core signals; and 
 a plurality of the I/O cells are typically to bond pads that in turn are connected to external pins, leads or soldier solder bumps on the IC's package. 
 
     
     
         31 . The semiconductor integrated circuit of  claim 20  further wherein:
 at least one of said I/O regions contains one or more programmable I/O cells; and 
 at least one interconnect cell contains programmable circuitry.