Analysis of chip-mean variation and independent intra-die variation for chip yield determination

Abstract

Systems and methods for determining a chip yield are disclosed. One method includes obtaining a first probability distribution function modeling variations within a chip and a second probability distribution function modeling variations between dies. Further, a discontinuous first level integration is performed with the first probability distribution function and a continuous second level integration is performed by a hardware processor based on the second probability function to determine the chip yield.

1 . A method for determining a chip yield comprising:
 obtaining a first probability distribution function modeling variations within a chip and a second probability distribution function modeling variations between dies;   performing a discontinuous first level integration with the first probability distribution function; and   performing, by a hardware processor, a continuous second level integration based on the second probability function to determine the chip yield.   
     
     
         2 . The method of  claim 1 , wherein the first probability distribution function is based on a first plurality of random variables and wherein the second probability distribution function is based on second plurality of random variables. 
     
     
         3 . The method of  claim 2 , wherein the first plurality of random variables account for variations between elements of an array of the chip. 
     
     
         4 . The method of  claim 2 , wherein the first level integration is based on a chip success function that nullifies the first probability distribution function at values of the first and second pluralities of random variables if a cell fails at said values. 
     
     
         5 . The method of  claim 1 , wherein the performing the discontinuous first level integration implements a Monte Carlo method. 
     
     
         6 . The method of  claim 1 , wherein the performing the discontinuous first level integration implements a boundary search method. 
     
     
         7 . The method of  claim 1 , wherein the performing the continuous second level integration further comprises performing a stochastic collocation. 
     
     
         8 . The method of  claim 7 , wherein the stochastic collocation is based on a sparse grid for random variables upon which the second probability distribution function is based. 
     
     
         9 . A method for determining an array yield for a chip comprising:
 generating sparse grid points for a first set of random variables modeling variations between dies;   for each of the sparse grid points, determining a cell yield by solving a first level integration with a first probability distribution function modeling variations within the chip; and   computing, by a hardware processor, the array yield for the chip by solving a second level integration based on the determined cell yields.   
     
     
         10 . The method of  claim 9 , wherein said computing comprises performing stochastic collocation. 
     
     
         11 . The method of  claim 10 , wherein said computing comprises performing a summation over the sparse grid points based on the cell yields. 
     
     
         12 . The method of  claim 11 , wherein the sparse grid points are sparse grid quadrature points and wherein terms of said summation include quadrature weights. 
     
     
         13 . The method of  claim 9 , wherein the first probability distribution function is based on a second set of random variables. 
     
     
         14 . The method of  claim 13 , wherein the second set of random variables account for variations between elements of an array of the chip. 
     
     
         15 . The method of  claim 14 , wherein the first level integration is based on a chip success function that nullifies the first probability distribution function at values of the first and second sets of random variables if a cell fails at said values. 
     
     
         16 . A method for determining a chip yield comprising:
 obtaining a first probability distribution function modeling variations within a chip and a second probability distribution function modeling variations between dies;   solving a first level integration problem based on the first probability distribution function at a first level solver;   transmitting cell yield functions from the first level solver through an interface to a second level solver; and   performing, by a hardware processor, at the second level solver, a second level integration based on the cell yield functions to determine the chip yield.   
     
     
         17 . The method of  claim 16 , wherein the method further comprises:
 selecting the first level solver from a plurality of first level solvers.   
     
     
         18 . The method of  claim 17 , wherein the interface is a common interface such that cell yield functions are receivable at the second level solver from each of said first level solvers through the common interface. 
     
     
         19 . The method of  claim 16 , wherein the method further comprises:
 adding the first level solver to a plurality of first level solvers from which cell yield functions are transmittable through said interface.   
     
     
         20 . The method of  claim 16 , wherein the method further comprises:
 modifying the first level solver.