Thin film transistor and manufacturing method thereof, array substrate, and display device

Abstract

The technical disclosure relates to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a base substrate, a gate electrode, an active layer, source/drain electrodes, a pixel electrode and one or more insulating layers, wherein at least one of the insulating layers comprises a bottom insulating sub-layer and a top insulating sub-layer, the top insulating sub-layer having a hydrogen content higher than that of the bottom insulating sub-layer.

What is claimed is: 
     
         1 . A thin film transistor, comprising: a base substrate, a gate electrode, an active layer, source/drain electrodes, a pixel electrode and one or more insulating layers, wherein at least one of the insulating layers comprises a bottom insulating sub-layer and a top insulating sub-layer, the top insulating sub-layer having a hydrogen content higher than that of the bottom insulating sub-layer. 
     
     
         2 . The thin film transistor according to  claim 1 , wherein the thin film transistor is an oxide thin film transistor, which comprises a plurality of insulating layers, the insulating layers comprising a gate insulating layer, an etch stop layer and a protective layer, the etch stop layer comprising a bottom etch stop layer as the bottom insulating sub-layer and a top etch stop layer as the top insulating sub-layer, the top etch stop layer having a hydrogen content higher than that of the bottom etch stop layer. 
     
     
         3 . The thin film transistor according to  claim 2 , wherein the hydrogen content of the top etch stop layer is 5%˜10%, and the hydrogen content of the bottom etch stop layer is 1%˜5%. 
     
     
         4 . The thin film transistor according to  claim 2 , wherein, in the oxide thin film transistor,
 the gate electrode is disposed on the base substrate;   the gate insulating layer covers the substrate and the gate electrode;   the active layer is disposed on the gate insulating layer corresponding to the gate electrode;   the bottom etch stop layer is disposed on the active layer;   the top etch stop layer is disposed on the bottom etch stop layer;   the source/drain electrodes are disposed on the top etch stop layer;   the protective layer covers the gate insulating layer, the source/drain electrodes and the top etch stop layer; and   the pixel electrode is disposed on the source/drain electrodes and the protective layer.   
     
     
         5 . The thin film transistor according to  claim 2 , wherein the bottom etch stop layer has a thickness of 200-1000 Å, and the top etch stop layer has a thickness of 1000-1500 Å. 
     
     
         6 . The thin film transistor according to  claim 2 , wherein the active layer is made of indium gallium zinc oxide semiconductor or indium zinc oxide semiconductor. 
     
     
         7 . An array substrate, comprising a thin film transistor according to  claim 1 . 
     
     
         8 . A display device, comprising an array substrate according to  claim 7 .