Semiconductor device including plural chips stacked to each other

Abstract

A device includes a plurality of Dynamic Random Access Memory (DRAM) chips in a stacked configuration connected by through silicon vias (TSVs), and each of the plurality of DRAM chips being configured to provide a local bank active signal to indicate when any one of a plurality of banks on a respective one of the plurality of DRAM chips is active, and local bank active signals from the plurality of DRAM chips being supplied through TSVs of intervening ones of the plurality of DRAM chips to a lowermost one of the plurality of DRAM chips.

What is claimed is: 
     
         1 . A device comprising:
 a plurality of Dynamic Random Access Memory (DRAM) chips in a stacked configuration connected by through silicon vias (TSVs), and   each of the plurality of DRAM chips being configured to provide a local bank active signal to indicate when any one of a plurality of banks on a respective one of the plurality of DRAM chips is active, and local bank active signals from the plurality of DRAM chips being supplied through TSVs of intervening ones of the plurality of DRAM chips to a lowermost one of the plurality of DRAM chips.   
     
     
         2 . The device as claimed in  claim 1  further comprising an interface chip stacked adjacent to the lowermost one of the plurality of DRAM chips and configured to receive the local bank active signals from the plurality of DRAM chips. 
     
     
         3 . The device as claimed in  claim 2  wherein the interface chip is configured to provide refresh commands to the plurality of DRAM chips only when the local bank active signals indicate that no banks are active in any one of the plurality of DRAM chips. 
     
     
         4 . The device as claimed in  claim 2  wherein the interface chip is configured to provide power down commands to the plurality of DRAM chips only when the local bank active signals indicate that no banks are active in any one of the plurality of DRAM chips. 
     
     
         5 . The device as claimed in  claim 1  wherein each of the plurality of DRAM chips comprises latch circuits, each latch circuit being set when a respective bank is activated and reset when the respective bank is precharged. 
     
     
         6 . The device as claimed in  claim 5  wherein all latch circuits within a selected one of the plurality of DRAM chips are reset when the selected one of the plurality of DRAM chips receives a precharge all command. 
     
     
         7 . The device as claimed in  claim 1  wherein the local bank active signals from the plurality of DRAM chips are supplied through cyclically connected TSVs of the intervening ones of the plurality of DRAM chips to the lowermost one of the plurality of DRAM chips.