Method of manufacturing semiconductor device

Abstract

A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.

1 - 20 . (canceled) 
     
     
         21 . A method of manufacturing a semiconductor device, comprising:
 forming a gate group including a plurality of gate patterns on a substrate;   forming a first spacer insulating layer on the gate group;   forming a spacer mask pattern on the first spacer insulating layer, side surfaces of the gate group disposed between side surfaces of the spacer mask pattern; and   etching the first spacer insulating layer using the spacer mask pattern as an etch mask.   
     
     
         22 . The method according to  claim 21 , wherein forming the first spacer insulating layer includes forming air gaps between the gate patterns. 
     
     
         23 . The method according to  claim 21 , wherein etching the first spacer insulating layer includes forming a first spacer including discontinuity points disposed on the side surfaces of the gate group. 
     
     
         24 . The method according to  claim 23 , wherein the discontinuity points is spaced from the gate group. 
     
     
         25 . The method according to  claim 23 ,
 wherein the discontinuity points includes a first discontinuity point disposed on a first side surface of the gate group and a second discontinuity point disposed on a second side surface of the gate group opposite the first side surface of the gate group, and   wherein a horizontal distance between the first discontinuity point and the first side surface of the gate group is the same as a horizontal distance between the second discontinuity point and the second side surface of the gate group.   
     
     
         26 . The method according to  claim 25 , wherein a vertical distance between the substrate and the first discontinuity point is the same as a vertical distance between the substrate and the second discontinuity points. 
     
     
         27 . The method according to  claim 21 , further comprising:
 forming a second spacer insulating layer on the first spacer insulating layer before forming the spacer mask pattern; and   etching the second spacer insulating layer using the spacer mask pattern.   
     
     
         28 . The method according to  claim 27 , wherein the second spacer insulating layer is denser than the first spacer insulating layer. 
     
     
         29 . The method according to  claim 21 , further comprising:
 forming a doping mask pattern on the gate group before the first spacer insulating layer;   doping the substrate with dopant using the doping mask pattern; and   removing the doping mask pattern.   
     
     
         30 . The method according to  claim 29 , wherein a width of the doping mask pattern is smaller than a width of the gate group. 
     
     
         31 . A method of manufacturing a semiconductor device, comprising:
 preparing a substrate including a cell region and a peripheral region;   forming a gate group including cell gate patterns and at least one selection gate pattern on the cell region of the substrate;   forming a peripheral gate pattern on the peripheral region of the substrate;   forming a first spacer insulating layer on the gate group and the peripheral gate pattern;   forming a cell mask pattern on the gate group, a width of the cell mask pattern being wider than a width of the gate group;   forming a peripheral mask pattern on the peripheral gate pattern, a width of the peripheral mask pattern being wider than a width of the peripheral gate pattern;   forming a first group spacer covering the gate group and a first pattern spacer covering the peripheral gate pattern by etching the first spacer insulating layer using the cell mask pattern and the peripheral mask pattern.   
     
     
         32 . The method according to  claim 31 ,
 wherein the first group spacer includes first inflection point and the first pattern spacer includes second inflection point, and   wherein a vertical distance between the substrate and the second inflection point is larger than a vertical distance between the substrate and the first inflection point.   
     
     
         33 . The method according to  claim 32 , wherein a horizontal distance between the first inflection point and the gate group is the same as a horizontal distance between the second inflection point and the peripheral gate pattern. 
     
     
         34 . The method according to  claim 32 , further comprising:
 forming a second spacer insulating layer on the first spacer insulating layer before forming the cell mask pattern and the peripheral mask pattern; and   forming a second group spacer on the first group spacer and a second pattern spacer on the second pattern spacer by etching the first spacer insulating layer and the second spacer insulating layer using the cell mask pattern and the peripheral mask pattern,   wherein the second group spacer is disposed above the first inflection point, and   wherein the second pattern spacer is disposed above the second inflection point.   
     
     
         35 . The method according to  claim 31 , further comprising:
 removing the cell mask pattern and the peripheral mask pattern after forming the first group spacer and the first pattern spacer;   forming a polishing stopper on the first group spacer and the first pattern spacer; and   forming an interlayer insulating layer on the polishing stopper.   
     
     
         36 . The method according to  claim 31 , wherein a horizontal length of a lower surface of the first group spacer is the same as a horizontal length of a lower surface of the first pattern spacer. 
     
     
         37 . A method of manufacturing a semiconductor device, comprising:
 forming a gate group including a first selection line, a second selection line and a word lines between the first selection line and the second selection line;   forming a first spacer insulating layer on the gate group;   forming a mask pattern on the first spacer, the mask pattern including a first side surface disposed outside the first selection line of the gate group, and a second side surface disposed outside the second selection line of the gate group;   forming a first spacer covering a top surface and side surfaces of the gate group by etching the first spacer insulating layer using the mask pattern,   wherein the first spacer including a first discontinuity point disposed near the first selection line and a second discontinuity point disposed near the second selection line.   
     
     
         38 . The method according to  claim 37 ,
 wherein a horizontal distance between the first selection line of the gate group and the first side surface of the mask pattern is larger than a horizontal distance between the second selection line of the gate group and the second side surface of the mask pattern, and   wherein a horizontal distance between the first selection line of the gate group and the first discontinuity point of the first spacer is larger than a horizontal distance between the second selection line of the gate group and the second discontinuity point of the first spacer.   
     
     
         39 . The method according to  claim 38 , wherein a level of the first discontinuity point is lower than a level of the second discontinuity point. 
     
     
         40 . The method according to  claim 38 , wherein a horizontal length of a lower surface of the first spacer disposed on the first selection line is the same as a horizontal length of a lower surface of the first spacer disposed on the second selection line.