Multiprocessor Computer System and Method Having at Least One Processor with a Dynamically Reconfigurable Instruction Set

Abstract

An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays.

1 . A method for representing a logical or physical technology, comprising:
 providing a first type system for describing a logic or physical technology, wherein the first type system comprises a state, at least one operator, and a persistence;   augmenting the state of the first type system;   augmenting the at least one operator of the first type system; and   augmenting the persistence of the first type system;   wherein the augmented stated, the augmented at least one operator and the augmented persistence creates a second type system.   
     
     
         2 . A method for synthesizing an embodiment in realizable devices from a behavioral specification of a design, the method comprising:
 adding to a design specification additional state information used in an embodiment as realizable devices, wherein the design specification comprises a plurality of types and subtypes representing a behavioral specification independent of an embodiment of tools implementing a synthesis process and independent of a specific design specification;   specifying an embodiment of operators as realizable devices independent of the embodiment of tools implementing the synthesis process and independent of the specific design specification;   representing an embodiment of persistent state instantiated from types and subtypes used in the specification and independent of the embodiment of tools implementing the synthesis process and independent of the specific design specification using a subprogram; and combining a behavioral specification with the steps of adding, specifying and representing, the combination yielding an embodiment of the behavioral specification as realizable devices.   
     
     
         3 . The method from  claim 2 , further comprising:
 selecting with a synthesis tool among alternative augmentations of state wherein each alternative augmentation is defined independent of an embodiment of tools implementing a synthesis process and independent of the specific design specification so as to optimize characteristics of a resulting embodiment.   
     
     
         4 . The method from  claim 2 , further comprising:
 selecting with a synthesis tool among alternative implementations of a type or subtype operator wherein each alternative implementation is defined independent of an embodiment of tools implementing a synthesis process and independent of the specific design specification so as to optimize characteristics of a resulting embodiment.   
     
     
         5 . A method for verifying that an embodiment in electronic devices matches a behavioral specification, the method comprising:
 adding to a design specification additional state information used in an embodiment as realizable devices,   wherein the design specification comprises a plurality of types and subtypes representing a behavioral specification independent of an embodiment of tools implementing a verification process and independent of a specific design specification;   specifying an embodiment of operators as realizable devices independent of the embodiment of tools implementing the verification process and independent of the specific design specification;   representing an embodiment of persistent state instantiated from types and subtypes used in the specification and independent of the embodiment of tools implementing the verification process using a subprogram; and   combining a behavioral specification with the steps or adding, specifying and representing, the combination yielding a simulation predicting behavior of a behavioral specification.   
     
     
         6 . A method comprising:
 initiating an executable file for processing instructions of the executable file by a multiprocessor system, wherein the multiprocessor system comprises at least one host processor and at least one dynamically reconfigurable co-processor;   determining one of a plurality of fixed instruction set images to load to said at least one dynamically reconfigurable co-processor for processing a portion of the instructions of the executable file, wherein the determined instruction set image defines an instruction set that differs from an instruction set of the at least one host processor, and wherein the determined instruction set image is not embedded within the executable file;   when determined that the determined instruction set image is not present on the dynamically reconfigurable co-processor, loading the determined instruction set image from persistent storage to the dynamically reconfigurable co-processor; and   processing, by the multiprocessor system, the instructions of the executable file, wherein a portion of the instructions are processed by the at least one host processor and a portion of the instructions are processed by the at least one dynamically reconfigurable co-processor.   
     
     
         7 . The method of  claim 6  further comprising:
 determining whether the determined instruction set image is present on the dynamically reconfigurable co-processor. 
 
     
     
         8 . The method of  claim 6  wherein determining the instruction set image to load to said at least one dynamically reconfigurable co-processor comprises:
 determining the instruction set image from information included in the executable file. 
 
     
     
         9 . The method of  claim 8  wherein the information included in the executable file identifies one of the plurality of fixed instruction set images. 
     
     
         10 . The method of  claim 9  wherein each of said plurality of fixed instruction set images is optimized for processing a corresponding class of operations. 
     
     
         11 . The method of  claim 10  wherein said plurality of fixed instruction set images comprise at least one of the following:
 a vector instruction set designed for efficiently processing 64-bit floating point operations; 
 a vector instruction set designed for efficiently processing 32-bit floating point operations; 
 an instruction set designed for efficiently processing cryptography-related operations; 
 an instruction set designed for efficiently performing operations for manipulating bit or byte strings; 
 an instruction set designed for efficiently performing computer-aided simulation operations; and 
 an instruction set designed for efficiently performing image processing operations. 
 
     
     
         12 . The method of  claim 6  wherein said instruction set of the at least one host processor is fixed within said at least one host processor. 
     
     
         13 . The method of  claim 12  wherein said instruction set of the at least one host processor is an x86 instruction set. 
     
     
         14 . A multiprocessor system comprising:
 a host processor comprising a first fixed instruction set;   persistent data storage for storing a plurality of different fixed instruction sets that differ from said first fixed instruction set, each of said plurality of different fixed instruction sets optimized for processing a corresponding class of operations; and   a co-processor comprising reconfigurable logic for dynamically reconfiguring the coprocessor's instruction set to a selected one of the plurality of different fixed instruction sets,   wherein said host processor and said co-processor are operable to process instructions of an executable file, and   wherein each of said plurality of different fixed instruction sets resides external to said executable file.   
     
     
         15 . The multiprocessor system of  claim 14  further comprising:
 each of said host processor and co-processor comprising a respective local caches wherein cache coherency is maintained between the host processor and co-processor. 
 
     
     
         16 . The multiprocessor system of  claim 14  further comprising:
 said host processor and said co-processor having a common virtual address space. 
 
     
     
         17 . A multiprocessor system comprising:
 a host processor;   a heterogeneous co-processor;   and said host processor and said heterogeneous co-processor having a common virtual address space.   
     
     
         18 . The multiprocessor system of  claim 17  further comprising:
 said co-processor comprising reconfigurable logic for dynamically reconfiguring the coprocessor's instruction set to any of a plurality of fixed instruction sets. 
 
     
     
         19 . The multiprocessor system of  claim 17  further comprising:
 an executable file comprising instructions, wherein a portion of said instructions are for processing by said host processor and a portion of said instructions are for processing by said coprocessor. 
 
     
     
         20 . The multiprocessor system of  claim 18  wherein all memory addresses for all of said instructions in the executable are virtual addresses. 
     
     
         21 . The method of  claim 6  wherein said determined instruction set image defines an extended instruction set that extends the instruction set of the at least one host processor. 
     
     
         22 . The method of  claim 6  wherein said loading comprises:
 loading the determined instruction set image to the co-processor before beginning execution of any of said instructions of the executable file by said at least one host processor and said at least one dynamically reconfigurable co-processor. 
 
     
     
         23 . The multi-processor system of  claim 17  further comprising:
 said co-processor comprising reconfigurable logic for dynamically reconfiguring the coprocessor's instruction set to any of a plurality of predefined extended instruction sets, 
 wherein each of said plurality of predefined extended instruction sets extends an instruction set of said host processor, and 
 wherein each of said plurality of predefined extended instruction sets is not embedded within an executable file that comprises a first segment of instructions for said instruction set of the host processor and a second segment of instructions for one of the plurality of predefined extended instruction sets. 
 
     
     
         24 . A multi-processor system comprising:
 a host processor comprising a first instruction set;   a co-processor comprising reconfigurable logic for dynamically reconfiguring the coprocessor's instruction set to a selected one of a plurality of predefined extended instruction sets for extending the first instruction set of the host processor;   persistent data storage for storing, separate from an executable file that comprises a first segment of instructions for a first instruction set and a second segment of instructions for one of the plurality of predefined extended instruction sets, said plurality of different predefined extended instruction sets; and   wherein, responsive to said executable file being initiated, said system is configured to identify said one of the plurality of predefined extended instruction sets, determine whether the identified predefined extended instruction set is present on the co-processor, when determined that the identified predefined extended instruction set is not present on the co-processor, load the identified predefined extended instruction set to the coprocessor, and   process the instructions of the executable file, wherein said first segment of the instructions are processed by the host processor and said second segment of the instructions are processed by the co-processor.   
     
     
         25 . The system of  claim 24  wherein said multi-processor system further comprises:
 an operating system, wherein said operating system is configured to perform said identify said one of the plurality of predefined extended instruction sets. 
 
     
     
         26 . The system of  claim 25  wherein said system is configured to perform said load of the identified predefined extended instruction set to the co-processor before beginning execution of said executable file by said host processor and said co-processor. 
     
     
         27 . The system of  claim 24  wherein said system is configured to:
 perform said load of the identified predefined extended instruction set to the coprocessor once for said second segment of instructions, where said second segment of instructions comprises a plurality of instructions for said identified one of the plurality of predefined extended instruction sets, rather than performing said load on an instruction-by-instruction basis for said plurality of instructions in said second segment. 
 
     
     
         28 . The system of  claim 24  wherein said second segment of instructions comprises a plurality of instructions for said identified one of the plurality of predefined extended instruction sets, and wherein said system is configured to:
 perform said load of the identified predefined extended instruction set to the coprocessor once for said executable file. 
 
     
     
         29 . The system of  claim 24  wherein each of said predefined extended instruction sets supports a plurality of different instructions that are optimized for processing a corresponding class of operations, wherein said system is configured to:
 perform said load of the identified predefined extended instruction set to the coprocessor for configuring the co-processor to have the full identified predefined extended instruction set for processing any of said plurality of different instructions of the identified predefined extended instruction set that are included in said second segment. 
 
     
     
         30 . A method comprising:
 identifying, in an executable file that comprises at least a first segment of instructions for a first instruction set and at least a second segment of instructions for a predefined extended instruction set, said predefined extended instruction set;   determining whether the identified predefined extended instruction set is present on a dynamically reconfigurable co-processor of a multi-processor system that comprises a host processor having said first instruction set and said dynamically reconfigurable co-processor that is reconfigurable to have any of a plurality of predefined extended instruction sets;   when determined that the identified predefined extended instruction set is not present on the dynamically reconfigurable co-processor, loading the identified predefined extended instruction set, from a file that is stored to persistent storage and that is separate from said executable file, to the dynamically reconfigurable co-processor; and   processing, by the multi-processor system, the instructions of the executable file, wherein said first segment of the instructions are processed by the host processor and said second segment of the instructions are processed by the dynamically reconfigurable coprocessor.   
     
     
         31 . (canceled) 
     
     
         32 . (canceled) 
     
     
         33 . (canceled) 
     
     
         34 . (canceled) 
     
     
         35 . (canceled) 
     
     
         36 . (canceled) 
     
     
         37 . The method of  claim 31  wherein the first instruction set is a fixed instruction set. 
     
     
         38 . A multiprocessor system comprising:
 one or more general purpose processors;   one or more target processors;   a library comprising one or more packages, each package comprising types, subtypes, constants and attribute/attribute specifications of a base architecture optimized for one or more specific processing operations of the one or more target processors, and the library further comprising one or more entity/architectures or configurations representing at least an instruction decode and one or more other functional units of the target processor;   one or more programmable logic arrays configured as at least one target processor;   wherein the one or more general purpose processors and the one or more target processors execute processing instructions.   
     
     
         39 . The multiprocessor system of  claim 38  further comprising;
 the one or more general purpose processors and the one or more target processors having access to the library. 
 
     
     
         40 . A multiprocessor system comprising:
 a general purpose processor;   a coprocessor comprising a programmable logic array having a dynamic or static specific set of cell designs and routing options;   a database accessible to the general purpose processor and the coprocessor.   
     
     
         41 . The multiprocessor system of  claim 40  further comprising:
 program instructions, some of which are executable on the general purpose processor and others that are executable on the coprocessor. 
 
     
     
         42 . The multiprocessor system of  claim 40  further comprising:
 the program instructions stored in the database. 
 
     
     
         43 . The multiprocessor system of  claim 40 ,
 wherein the cell designs and routing information extend logic and physical processing capability of the general purpose processor.