Scalable memory system

Abstract

A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

1 . A method comprising:
 receiving, at a memory device of a memory system having serially connected memory devices, a first command including a device address corresponding to the memory device;   executing at least one core operation in a first memory bank of the memory device in response to the first command;   receiving, at the memory device, a second command during execution of the at least one core operation in the first memory bank, the second command including the device address corresponding to the memory device; and,   executing, concurrently with the execution of one or more of the at least one core operation executed in the first memory bank, at least one core operation in a second memory bank of the selected memory device in response to the second command.   
     
     
         2 . The method of  claim 1 , further including
 receiving a third command for requesting result information from one of the first memory bank and the second memory bank, and   outputting a read data packet containing the result information in response to the third command.   
     
     
         3 . The method of  claim 2 , wherein the result information includes one of status register data and read data. 
     
     
         4 . The method of  claim 1 , wherein the first command and the second command are command packets including a series of bits logically configured to include:
 a mandatory command field for providing an operation code and a device address,   an optional address field following the command field for providing one of a row and column address when the operation code corresponds to a read or write operation, and,   an optional data field following the address field for providing write data when the operation code corresponds to the write operation.   
     
     
         5 . The method of  claim 4 , wherein
 a first command strobe is received in parallel with the first command, the first command strobe having an active duration corresponding to the length of the first command, and   a second command strobe is received in parallel with the second command, the second command strobe having an active duration corresponding to the length of the second command.   
     
     
         6 . The method of  claim 5 , wherein a data input strobe is received for enabling outputting of the read data packet while the data input strobe is at the active level. 
     
     
         7 . The method of  claim 6 , wherein the first command strobe and the second command strobe are separated by at least one data latching clock edge. 
     
     
         8 . The method of  claim 6 , wherein the second command strobe and data input strobe are separated by at least one data latching clock edge. 
     
     
         9 . The method of  claim 1 , further comprising initializing the memory device by generating device address and device identifier information for the memory device. 
     
     
         10 . A memory device configured to:
 receive a first command including a device address corresponding to the memory device;   execute at least one core operation in a first memory bank of the memory device in response to the first command;   receive a second command during execution of the at least one core operation in the first memory bank, the second command including the device address corresponding to the memory device; and   execute, concurrently with the execution of one or more of the at least one core operation executed in the first memory bank, at least one core operation in a second memory bank of the selected memory device in response to the second command.   
     
     
         11 . The memory device of  claim 10 , further configured to:
 receive a third command for requesting result information from one of the first memory bank and the second memory bank, and   output a read data packet containing the result information in response to the third command.   
     
     
         12 . The memory device of  claim 11 , wherein the result information includes one of status register data and read data. 
     
     
         13 . The memory device of  claim 10 , wherein the first command and the second command are command packets including a series of bits logically configured to include:
 a mandatory command field for providing an operation code and a device address,   an optional address field following the command field for providing one of a row and column address when the operation code corresponds to a read or write operation, and,   an optional data field following the address field for providing write data when the operation code corresponds to the write operation.   
     
     
         14 . The memory device of  claim 13 , wherein:
 a first command strobe is received in parallel with the first command, the first command strobe having an active duration corresponding to the length of the first command, and   a second command strobe is received in parallel with the second command, the second command strobe having an active duration corresponding to the length of the second command.   
     
     
         15 . The memory device of  claim 14 , wherein a data input strobe is received for enabling outputting of the read data packet while the data input strobe is at the active level. 
     
     
         16 . The memory device of  claim 15 , wherein the first command strobe and the second command strobe are separated by at least one data latching clock edge. 
     
     
         17 . The memory device of  claim 15 , wherein the second command strobe and data input strobe are separated by at least one data latching clock edge. 
     
     
         18 . The memory device of  claim 10 , further comprising initializing the memory device by generating device address and device identifier information for the memory device. 
     
     
         19 . A memory system having serially connected memory devices, wherein at least one of the memory devices is configured to:
 receive a first command including a device address corresponding to the at least one memory device;   execute at least one core operation in a first memory bank of the memory device in response to the first command;   receive a second command during execution of the at least one core operation in the first memory bank, the second command including the device address corresponding to the at least one memory device; and   execute, concurrently with the execution of one or more of the at least one core operation executed in the first memory bank, at least one core operation in a second memory bank of the selected memory device in response to the second command.