Scheduling and Traffic Management with Offload Processors

Abstract

A scheduling system for a packet processing system is disclosed. The system can include a classification circuit connected to a memory bus and configurable to classify network packets, placing the classified network packets into first multiple input/output queues, a scheduling circuit for reordering the network packets received from the classification circuit through the first multiple input/output queues and placing the reordered network packets into second multiple input/output queues, an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, and multiple offload processors, each coupled to at least one of the multiple output ports, the offload processors configured to modify the network packets.

What is claimed is: 
     
         1 . A scheduling system for a packet processing system, comprising:
 a classification circuit connected to a memory bus and configurable to classify network packets, placing the classified network packets into first multiple input/output queues,   a scheduling circuit for reordering the network packets received from the classification circuit through the first multiple input/output queues and placing the reordered network packets into second multiple input/output queues,   an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, and   multiple offload processors, each coupled to at least one of the multiple output ports, the offload processors configured to modify the network packets.   
     
     
         2 . The system of  claim 1  wherein the memory bus supports direct memory access, and the multiple offload processors can direct modified packets back to the memory bus. 
     
     
         3 . The system of  claim 1  wherein the classification circuit is configured to classify network packets based on session metadata. 
     
     
         4 . The system of  claim 1  wherein the scheduling circuit is configured to direct network packets based on availability of respective multiple offload processors. 
     
     
         5 . The system of  claim 1  wherein the scheduling circuit is configured to reorder network packets according to session priority. 
     
     
         6 . The system of  claim 1  wherein the scheduling circuit is configured to initiate a context switch for at least one of the multiple offload processors. 
     
     
         7 . The system of  claim 1  wherein the scheduling circuit is configured to transfer network packets into a defined traffic management queue. 
     
     
         8 . The system of  claim 1  wherein the scheduling circuit is configured to determine when network packet processing for each of the multiple offload processors is complete. 
     
     
         9 . The system of  claim 1  wherein the scheduling circuit is configured to operate in a preemption mode to control session execution. 
     
     
         10 . A scheduling system for a packet processing system, comprising:
 a classification circuit connected to a memory bus and configurable to classify network packets based on session metadata, and placing the classified network packets into first multiple input/output queues,   a scheduling circuit configured to reorder the network packets received from the classification circuit through the first multiple input/output queues and placing the classified network packets into second multiple input/output queues,   an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, and   multiple offload processors, each coupled to one of the multiple output ports, the offload processors configured to modify network packets and direct the modified packets to the memory bus.   
     
     
         11 . The system of  claim 10  wherein the scheduling circuit is configured to direct network packets based on availability of respective multiple offload processors. 
     
     
         12 . The system of  claim 10  wherein the scheduling circuit is configured to reorder network packets according to session priority of the network packets. 
     
     
         13 . The system of  claim 10  wherein the scheduling circuit is configured to initiate a context switch for at least one of the multiple offload processors. 
     
     
         14 . The system of  claim 10  wherein the scheduling circuit is configured to transfer network packets into a defined traffic management queue. 
     
     
         15 . The system of  claim 10  wherein the scheduling circuit is configured to determine when network packet processing for each of the multiple offload processors is complete. 
     
     
         16 . The system of  claim 10  wherein the scheduling circuit is configured to operate in a preemption mode to control session execution.