US2014198653A1PendingUtilityA1

Scheduling and Traffic Management with Offload Processors

61
Assignee: XOCKETS IP LLCPriority: Jan 17, 2013Filed: Jun 22, 2013Published: Jul 17, 2014
Est. expiryJan 17, 2033(~6.5 yrs left)· nominal 20-yr term from priority
H04L 49/90H04L 67/10H04L 2101/686H04L 67/1097Y02D10/00G06F 12/0815G06F 13/1652G06F 13/362H04L 47/6295G06F 13/4022G06F 13/4068H04L 47/56H04L 47/2441G06F 13/285G06F 9/461G06F 12/1081G06F 13/16G06F 15/161H04L 47/193H04L 47/624G06F 15/17337H04L 61/2592G06F 9/3877H04L 49/40G06F 9/4843G06F 12/1027G06F 2212/1024G06F 12/0875H04L 61/103
61
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Claims

Abstract

A method for scheduling packet processing is disclosed. The method can include classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with network packets transported to a classification circuit using a memory bus having a defined memory transport protocol, reordering network packets received from the first multiple input/output queues using a scheduling circuit and placing the reordered network packets into a second multiple input/output queues, directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports using an arbitration circuit, and modifying network packets using multiple offload processors, each offload processor coupled to at least one of the multiple output ports, the offload processors configured to direct modified network packets back to the memory bus.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for scheduling packet processing, comprising the steps of:
 classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with network packets transported to a classification circuit using a memory bus having a defined memory transport protocol,   reordering network packets received from the first multiple input/output queues using a scheduling circuit and placing the reordered network packets into a second multiple input/output queues,   directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports using an arbitration circuit, and   modifying network packets using multiple offload processors, each offload processor coupled to at least one of the multiple output ports, the offload processors configured to direct modified network packets back to the memory bus.   
     
     
         2 . The method of  claim 1  wherein the directing of network packets is based on availability of the multiple offload processors. 
     
     
         3 . The method of  claim 1  wherein the reordering of network packets is according to session priorities of the network packets. 
     
     
         4 . The method of  claim 1  further including initiating a context switch for at least one of the multiple offload processors by operation of the scheduling circuit. 
     
     
         5 . The method of  claim 1  further including transferring network packets into a defined traffic management queue by operation of the scheduling circuit. 
     
     
         6 . The method of  claim 1  further including determining when packet processing for each of the multiple offload processors is complete by operation of the scheduling circuit. 
     
     
         7 . The method of  claim 1  further including preempting a current network packet processing session by operation of the scheduling circuit.

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