Scheduling and Traffic Management with Offload Processors

Abstract

A memory bus connected module for scheduling services for network packet processing is disclosed. The module can include a memory bus connection, a scheduling circuit configured to reorder network packets received from the memory bus connection and place the reordered network packets into multiple input/output queues, and multiple offload processors connected to the memory bus connection, each offload processor configured to modify network packets in the multiple input/output queues.

What is claimed is: 
     
         1 . A memory bus connected module for scheduling services for network packet processing, the module comprising:
 a memory bus connection,   a scheduling circuit configured to reorder network packets received from the memory bus connection and place the reordered network packets into multiple input/output queues, and   multiple offload processors connected to the memory bus connection, each offload processor configured to modify network packets in the multiple input/output queues.   
     
     
         2 . The module of  claim 1  wherein the scheduling circuit is configured to direct network packets based on availability of respective multiple offload processors. 
     
     
         3 . The module of  claim 1  wherein the scheduling circuit is configured to reorder network packets according to a session priority of the network packets. 
     
     
         4 . The module of  claim 1  wherein the scheduling circuit is configured to initiate a context switch for at least one of the multiple offload processors. 
     
     
         5 . The module of  claim 1  wherein the scheduling circuit is configured to transfer network packets into a defined traffic management queue. 
     
     
         6 . The module of  claim 1  wherein the scheduling circuit is configured to determine when network packet processing for each of the multiple offload processors is complete. 
     
     
         7 . The module of  claim 1  wherein the scheduling circuit is configured to operate in a preemption mode to control session execution. 
     
     
         8 . The module of  claim 1 , wherein the memory bus connection is compatible with a memory bus socket. 
     
     
         9 . The module of  claim 1 , wherein the memory bus connection is compatible with a dual in line memory module (DIMM) socket.