Network Overlay System and Method Using Offload Processors

Abstract

An input-output (IO) virtualization system connectable to a network is disclosed. The system can include a second virtual switch connected to a memory bus and configured to receive network packets from a first virtual switch, and an offload processor module supporting the second virtual switch, the offload processor module further comprising at least one offload processor configured to modify network packets and direct the modified network packets to the first virtual switch through the memory bus.

What is claimed is: 
     
         1 . An input-output (IO) virtualization system connectable to a network, the system comprising:
 a second virtual switch connected to a memory bus and configured to receive network packets from a first virtual switch, and   an offload processor module supporting the second virtual switch, the offload processor module further comprising at least one offload processor configured to modify network packets and direct the modified network packets to the first virtual switch through the memory bus.   
     
     
         2 . The system of  claim 1  wherein the second virtual switch receives network packets via memory write operations on the memory bus and sends network packets via the memory read operations on the memory bus. 
     
     
         3 . The system of  claim 1 , wherein:
 the offload processor module comprises separately addressable offload processors, at least two of the offload processors being configured to process network packets directed to memory addresses corresponding to the offload processors.   
     
     
         4 . The system of  claim 1  wherein the memory bus supports a dual data rate (DDR) protocol. 
     
     
         5 . The system of  claim 4  wherein the protocol is DDR3. 
     
     
         6 . The system of  claim 1  wherein the first virtual switch is configured to communicate with the second virtual switch by direct memory accesses. 
     
     
         7 . The system of  claim 1  wherein the first virtual switch comprises a direct memory access (DMA) master. 
     
     
         8 . The system of  claim 1  wherein the second virtual switch comprises a direct memory access (DMA) slave. 
     
     
         9 . The system of  claim 1  wherein the second virtual switch comprises a scheduler and an arbiter to prioritize handling of network packets. 
     
     
         10 . An input-output (IO) virtualization system, comprising:
 a physical IO device,   multiple virtual IO devices, and   a provisioning agent configured to allocate address spaces in a main memory to each of the multiple virtual IO devices and the physical IO device, with each of the physical or virtual IO devices configured to execute direct memory reads and writes to their respective address spaces.   
     
     
         11 . The system of  claim 10  wherein the address spaces can be physical or virtual, and the provisioning agent is configured to create a mapping between virtual addresses and physical addresses. 
     
     
         12 . The system of  claim 10  further comprising multiple offload processors corresponding to a defined address space, and wherein the defined address spaces can be physical or virtual, and the provisioning agent can create a mapping between virtual addresses and physical addresses. 
     
     
         13 . The system of  claim 10 , wherein the provisioning agent is configured to allocate physical addresses for virtual function (VF) drivers. 
     
     
         14 . The system of  claim 10 , further including virtual function (VF) drivers configured to write at least a portion of a descriptor for network packet data processing. 
     
     
         15 . The system of  claim 10 , further including:
 the address spaces can be physical or virtual, and the provisioning agent is configured to create a mapping between virtual addresses and physical addresses, and   an input output memory management unit (IOMMU) having tables configured to store the mapping.   
     
     
         16 . The system of  claim 10  further including a plurality of virtual function (VF) drivers configured to support direct memory accesses to the second virtual switch. 
     
     
         17 . The system of  claim 9  wherein the provisioning agent is executed by at least one host processor.