Network Overlay System and Method Using Offload Processors

Abstract

A method for processing data is disclosed. The method can include transporting data to a second virtual switch from a first virtual switch using a memory bus having a defined memory transport protocol, writing the transported data to a target memory location, and processing the data written to the target memory location with at least one offload processor included on an offload processor module.

What is claimed is: 
     
         1 . A method for processing data, comprising the steps of”
 transporting data to a second virtual switch from a first virtual switch using a memory bus having a defined memory transport protocol, 
 writing the transported data to a target memory location, and 
 processing the data written to the target memory location with at least one offload processor included on an offload processor module. 
 
     
     
         2 . The method of  claim 1 , further including sending data processed by the at least one offload processor to first virtual switch via the second virtual switch. 
     
     
         3 . The method of  claim 1 , wherein transporting data to the second virtual switch includes a memory write operation to a physical memory address corresponding to a virtual memory address determined by the first virtual switch. 
     
     
         4 . The method of  claim 1 , wherein processing the data written to the target memory location includes processing data at specific memory addresses by offload processors corresponding to such specific memory addresses. 
     
     
         5 . The method of  claim 1  wherein transporting data to the second virtual switch includes transporting the data over a memory bus using a double data rate (DDR) protocol. 
     
     
         6 . The method of  claim 5  wherein the DDR protocol is the DDR3 protocol. 
     
     
         7 . The method of  claim 1  wherein transporting data to the second virtual switch includes a direct memory access operation. 
     
     
         8 . The method of  claim 1  wherein transporting data to the second virtual switch includes operating the first virtual switch as a direct memory access (DMA) master. 
     
     
         9 . The method of  claim 1  wherein transporting data to the second virtual switch includes operating the second virtual switch as a direct memory access (DMA) slave. 
     
     
         10 . The method of  claim 1  wherein processing the data includes prioritizing from among multiple data values. 
     
     
         11 . The method of  claim 10  wherein prioritizing from among multiple data values includes scheduling the processing of the data for particular offload processors by operation of a scheduler. 
     
     
         12 . The method of  claim 10  wherein prioritizing from among multiple data values includes arbitrating access to the data written by operation of an arbiter. 
     
     
         13 . The method of  claim 1  further including;
 examining data received at the first virtual switch to identify a first target memory address; and 
 generating the second target memory address from the first target memory address. 
 
     
     
         14 . The method of  claim 14  wherein the first target memory address is a virtual address and the second target memory address is a physical address.