US2014201305A1PendingUtilityA1

Network Overlay System and Method Using Offload Processors

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Assignee: XOCKETS IP LLCPriority: Jan 17, 2013Filed: Jun 24, 2013Published: Jul 17, 2014
Est. expiryJan 17, 2033(~6.5 yrs left)· nominal 20-yr term from priority
H04L 49/90H04L 2101/686H04L 67/1097H04L 67/10Y02D10/00G06F 13/285H04L 47/56G06F 12/1081G06F 9/4843G06F 2212/1024G06F 13/1652H04L 47/6295H04L 47/624H04L 47/2441H04L 61/2592G06F 13/4022H04L 61/103H04L 49/40G06F 13/16G06F 12/0815G06F 12/0875G06F 15/17337G06F 13/362G06F 9/461G06F 12/1027G06F 13/4068G06F 15/161H04L 47/193G06F 9/3877H04L 67/2842
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Claims

Abstract

A memory bus connected module, connectable to a first virtual switch for providing input-output (IO) virtualization services is disclosed. The module can include a second virtual switch coupled to the first virtual switch via a memory bus connection, a plurality of offload processors coupled to the memory bus connection, and at least one memory unit connected to, and separately addressable by, the multiple offload processors, and configured to receive data directed to a specific memory address space for processing by at least one of the offload processors.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A memory bus connected module, connectable to a first virtual switch for providing input-output (IO) virtualization services, the module comprising:
 a second virtual switch coupled to the first virtual switch via a memory bus connection,   a plurality of offload processors coupled to the memory bus connection, and   at least one memory unit connected to, and separately addressable by, the multiple offload processors, and configured to receive data directed to a specific memory address space for processing by at least one of the offload processors.   
     
     
         2 . The module of  claim 1 , further comprising an arbiter configured to prevent memory access conflicts to the at least one memory unit. 
     
     
         3 . The module of  claim 1 , wherein the module is configured to receive data at the second virtual switch by memory writes of a system and to send data at the second virtual switch by memory reads of the system. 
     
     
         4 . The module of  claim 1 , wherein the module is configured to receive the data by direct memory access operations. 
     
     
         5 . The module of  claim 1 , wherein the module comprises a direct memory access (DMA) slave. 
     
     
         6 . The module of  claim 1 , wherein the memory bus connection is compatible with a dual in line memory (DIMM) socket. 
     
     
         7 . A method for providing IO virtualization services using a memory bus connected module comprising a second virtual switch connectable to a first virtual switch, comprising the steps of:
 transferring data to an addressable memory unit supported by the memory bus connected module, and   transferring data to multiple offload processors supported by the memory bus connected module using specific memory address spaces in the memory unit, each address space corresponding to a different offload processor.   
     
     
         8 . The method of  claim 7 , further comprising arbitrating memory unit access conflicts by operation an arbiter supported by the memory bus connected module. 
     
     
         9 . The method of  claim 7 , further comprising receiving and sending data through direct memory access (DMA) reads and writes via the memory bus connection 
     
     
         10 . The method of  claim 7 , further comprising allocating virtual memory addresses that correspond to specific memory address spaces in the memory unit. 
     
     
         11 . The method of  claim 7 , wherein transferring data includes transferring data to the memory bus connected module through a memory bus socket. 
     
     
         12 . The method of  claim 7 , wherein transferring data includes transferring data to the memory bus connected module through a dual in line memory module (DIMM) compatible socket.

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