US2014201390A1PendingUtilityA1
Network Overlay System and Method Using Offload Processors
Est. expiryJan 17, 2033(~6.5 yrs left)· nominal 20-yr term from priority
H04L 49/90H04L 67/1097H04L 2101/686H04L 67/10Y02D10/00G06F 13/1652G06F 13/4022G06F 2212/1024H04L 47/6295H04L 49/40G06F 12/1081H04L 47/2441G06F 9/4843G06F 15/161H04L 61/103G06F 12/1027G06F 13/16G06F 13/4068H04L 61/2592G06F 13/362H04L 47/56G06F 12/0875G06F 12/0815H04L 47/624G06F 15/17337H04L 47/193G06F 9/461G06F 13/285G06F 9/3877
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Claims
Abstract
A network overlay system capable of processing network packets having metadata is disclosed. The system can include a data transport module configurable to direct network packets based on network identifier tags, an offload processor module connected to a memory bus and including at least one offload processor capable of modifying segregated network packets, and a memory bus connected between the data transport module and the at least one offload processor to support transport of network packets to the offload processor for modification.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A network overlay system capable of processing network packets having metadata, the system comprising:
a data transport module configurable to direct network packets based on network identifier tags, an offload processor module connected to a memory bus and including at least one offload processor capable of modifying segregated network packets, and a memory bus connected between the data transport module and the at least one offload processor to support transport of network packets to the offload processor for modification.
2 . The system of claim 1 wherein the data transport module includes an address translation module.
3 . The system of claim 1 wherein the data transport module includes a network card programmable to identifying network identifier tags of packets.
4 . The system of claim 1 wherein the data transport module includes an input output memory management unit (IOMMU) to translate virtual addresses to corresponding physical addresses.
5 . The system of claim 1 wherein the memory bus supports a double data rate (DDR) protocol.
6 . The system of claim 5 , wherein the DDR protocol is DDR3.
7 . The system of claim 1 wherein the data transport module receives information from a packet network.
8 . The system of claim 1 wherein the data transport module receives information from a switched network.
9 . The system of claim 1 wherein the data transport module is configured to direct packets to a specific memory address space for processing by at least one specified offload processor.
10 . The system of claim 1 wherein the offload processor module includes multiple general purpose offload processors to support parallel execution of tasks on received network packets.
11 . A network overlay system capable of processing network packets with metadata, the system comprising:
a data transport module configurable to direct network packets based on network identifier tags, an offload processor module including multiple general purpose offload processors, each offload processor capable of modifying network packets, control logic for determining respective task execution by the multiple general purpose offload processors, and a memory bus connected between the data transport module and at least one offload processor to support transport of network packets to the at least one offload processor for modification.
12 . The system of claim 11 wherein the data transport module includes an address translation module.
13 . The system of claim 11 wherein the control logic includes a scheduler that is updated as network packet data is received.
14 . The system of claim 11 wherein the data transport module includes an input output memory management unit (IOMMU) to translate virtual addresses to physical addresses.
15 . The system of claim 11 wherein the offload processor module includes a buffer memory accessible through an arbiter logic unit.
16 . The system of claim 11 wherein the offload processor module includes a switch controller for determining context switch of the multiple general purpose offload processors.
17 . The system of claim 11 wherein the data transport module receives information from a switched network.
18 . The system of claim 11 wherein the data transport module is configured to direct packets to a specific memory address space for processing by at least one specified offload processor.Cited by (0)
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