Context Switching with Offload Processors

Abstract

A memory bus connected module with context switching capability is described. The module can include a memory bus connection compatible with a memory bus socket, a plurality of offload processors attached to the module and connected to a memory bus, with each offload processor having a cache with an associated cache state, a context memory attached to the module and connected to the offload processors, and a scheduling circuit configured to direct a transfer of a cache state between at least one of the offload processors and the context memory.

What is claimed is: 
     
         1 . A memory bus connected module with context switching capability, the module comprising:
 a memory bus connection compatible with a memory bus socket,   a plurality of offload processors attached to the module and connected to a memory bus, with each offload processor having a cache with an associated cache state,   a context memory attached to the module and connected to the offload processors, and   a scheduling circuit configured to direct a transfer of a cache state between at least one of the offload processors and the context memory.   
     
     
         2 . The module of  claim 1  wherein at least one of the offload processors each have an accelerator coherency port for accessing cache state. 
     
     
         3 . The module of  claim 1  wherein the associated cache state includes at least one selected from the group of: a state of offload processor registers, instructions for execution by an offload processor, a stack pointer, program counter, prefetched instructions for execution by the offload processor, prefetched data for use by the offload processor, and data written into the cache of the offload processor. 
     
     
         4 . The module of  claim 1 , wherein:
 at least one offload processor is configured to run an operating system (OS); and   the scheduling circuit is configured to cooperate with the OS to set context for a processing session to be physically contiguous in the cache of the offload processor.   
     
     
         5 . The module of  claim 1 , wherein:
 at least one offload processor is configured to run an operating system (OS); and   the scheduling circuit is configured to cooperate with the OS to set a processing session size and starting physical address in the cache of the offload processor.   
     
     
         6 . The module of  claim 1 , wherein:
 at least one offload processor is configured to run an operating system (OS); and   the scheduling circuit is configured to cooperate with an OS to set a processing session color.   
     
     
         7 . The module of  claim 1 , further including a memory allocator configured to determining starting cache address of each of multiple processing sessions, the number of sessions allowable in a cache, and the number of locations wherein a session can be found for a given color in a cache. 
     
     
         8 . The module of  claim 7 , wherein the memory allocator is formed from a system portion selected from: the OS and the scheduler circuit. 
     
     
         9 . The module of  claim 1 , wherein the scheduling circuit is configured to direct transfer of a cache state of one offload processor to the cache of another offload processor. 
     
     
         10 . The module of  claim 1  wherein the scheduling circuit is configured to operate in preemption mode to control session execution in a system. 
     
     
         11 . The module of  claim 10 , wherein the memory bus connection is compatible with a dual in-line memory module (DIMM) socket. 
     
     
         12 . The module of  claim 1 , wherein the scheduling circuit is configured to direct transfer of the cache state over the memory bus. 
     
     
         13 . The module of  claim 1 , wherein the context memory comprises at least one low latency memory device.