Context Switching with Offload Processors

Abstract

A method for context switching of multiple offload processors coupled to receive data for processing over a memory bus is disclosed. The method can include directing storage of a cache state, via a bulk read from a cache of at least one of a plurality of offload processors into a context memory, by operation of a scheduling circuit, with any virtual and physical memory locations of the cache state being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing, by operation of the scheduling circuit.

What is claimed is: 
     
         1 . A method for context switching of multiple offload processors coupled to receive data for processing over a memory bus, comprising the steps of:
 directing storage of a cache state, via a bulk read from a cache of at least one of a plurality of offload processors into a context memory, by operation of a scheduling circuit, with any virtual and physical memory locations of the cache state being aligned, and   subsequently directing transfer of the cache state to at least one of the offload processors for processing, by operation of the scheduling circuit.   
     
     
         2 . The method of  claim 1  wherein the bulk read is through an accelerator coherency port. 
     
     
         3 . The method of  claim 1  wherein the associated cache state includes at least one of: a state of offload processor registers, instructions for execution by the offload processor, a stack pointer, program counter, prefetched instructions for execution by the offload processor, prefetched data for use by the offload processor, and data written into the cache of the offload processor. 
     
     
         4 . The method of  claim 1 , further including:
 the cache state includes session context; and   setting the session context to be physically contiguous in the cache of the offload processor.   
     
     
         5 . The method of  claim 4 , wherein the setting of the session context includes cooperation of an operating system (OS) running on the offload processor and the scheduling circuit. 
     
     
         6 . The method of  claim 1 , further including upon initialization of a processing session, communicating session data to the scheduling circuit. 
     
     
         7 . The method of  claim 6 , wherein the session data includes any selected from: a session color, a session size and starting physical cache address for the processing session. 
     
     
         8 . The method of  claim 1 , further including
 determining starting address for each of a plurality of processing sessions, the number of sessions allowable in a cache of an offload processor, and the number of locations wherein a session can be found for a given session color.   
     
     
         9 . The method of  claim 1  further including transferring the cache state of one of the offload processors to the cache of another of the offload processors. 
     
     
         10 . The method of  claim 1 , further including prioritizing a processing of network packets in a first queue received over the memory bus by stopping a first session associated with one of the offload processors, storing the cache state of the offload processor, and initiating processing of network packets held in a second queue. 
     
     
         11 . The method of  claim 1  further including setting a session context of a processing executed by an offload processor to be physically contiguous in the cache of the offload processor. 
     
     
         12 . The method of  claim 1  wherein the bulk read from the cache into the context memory includes a bulk read into a low latency memory device. 
     
     
         13 . The method of  claim 1  wherein the bulk read from the cache into the context memory includes a bulk read over the memory bus.