US2014201761A1PendingUtilityA1
Context Switching with Offload Processors
Est. expiryJan 17, 2033(~6.5 yrs left)· nominal 20-yr term from priority
H04L 49/90H04L 67/1097H04L 2101/686H04L 67/10Y02D10/00G06F 13/285G06F 9/4843H04L 47/6295G06F 13/4068G06F 13/16G06F 13/362G06F 12/0815G06F 2212/1024H04L 61/2592G06F 12/1027H04L 47/193G06F 13/1652H04L 47/624G06F 12/1081G06F 13/4022G06F 15/161H04L 47/56H04L 61/103G06F 9/3877G06F 15/17337H04L 49/40G06F 9/461H04L 47/2441G06F 12/0875
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Claims
Abstract
A method for context switching of multiple offload processors is disclosed. The method can include receiving network packets for processing through a memory bus connected socket, organizing the network packets into multiple sessions for processing, suspending processing of at least one session by reading a cache state of at least one of the offload processor into a context memory by operation of a scheduling circuit, with virtual memory locations and physical cache locations being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing by operation of the scheduling circuit.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for context switching of multiple offload processors, comprising the steps of:
receiving network packets for processing through a memory bus connected socket, organizing the network packets into multiple sessions for processing, suspending processing of at least one session by reading a cache state of at least one of the offload processor into a context memory by operation of a scheduling circuit, with virtual memory locations and physical cache locations being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing by operation of the scheduling circuit.
2 . The method of claim 1 wherein the bulk read is through an accelerator coherency port.
3 . The method of claim 1 wherein the associated cache state includes at least one of: a state of offload processor registers, instructions for execution by the offload processor, a stack pointer, program counter, prefetched instructions for execution by the offload processor, prefetched data for use by the offload processor, and data written into the cache of the offload processor.
4 . The method of claim 1 , further including:
the cache state includes session context; and setting the session context to be physically contiguous in the cache of the offload processor.
5 . The method of claim 4 , wherein the setting of the session context includes cooperation of an operating system (OS) running on the offload processor and the scheduling circuit.
6 . The method of claim 1 , further including upon initialization of a processing session, communicating session data to the scheduling circuit.
7 . The method of claim 6 , wherein the session data includes any selected from: a session color, a session size and starting physical cache address for the processing session.
8 . The method of claim 1 , further including
determining starting address for each of a plurality of processing sessions, the number of sessions allowable in a cache of an offload processor, and the number of locations wherein a session can be found for a given session color.
9 . The method of claim 1 further including
transferring the cache state of one of the offload processors to the cache of another of the offload processors.
10 . The method of claim 1 , further including prioritizing a processing of network packets in a first queue received over the memory bus by stopping a first session associated with one of the offload processors, storing the cache state of the offload processor, and initiating processing of network packets held in a second queue.
11 . The method of claim 1 , wherein the suspending processing of at least one session includes operating in a preemption mode to control a session execution.
12 . The method of claim 1 , wherein receiving network packets includes receiving network packets through a dual in line memory module (DIMM) compatible socket.
13 . The method of claim 1 , wherein reading the cache state into the context memory includes reading the cache state data over the memory bus.Cited by (0)
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