Robust Initialization with Phase Change Memory Cells in Both Configuration and Array

Abstract

The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data.

1 - 20 . (canceled) 
     
     
         21 . A memory connectable to be powered from a supply voltage, comprising:
 at least one redundancy data storage comprising a plurality of phase change memory cells;   at least one array of phase change memory cells;   at least one access logic controlling access to said array and operating in at least partial dependence on redundancy data stored in said redundancy data storage; and   a voltage qualification unit configured to detect whether the supply voltage causes reads of a plurality of phase change memory reference cells to produce correctly distinct outputs to different logic states stored in said reference cells,   wherein said redundancy data storage is operatively connected to enable said access logic only after said voltage qualification unit has detected said correctly distinct outputs;   configuration logic which loads configuration information from a phase change memory into a volatile memory, said configuration information residing in said phase change memory when power to the memory is OFF, said configuration information at least partially determining one or more operation parameters of said memory, wherein said voltage qualification unit is configured to allow said configuration logic to begin loading configuration information only after said voltage qualification unit has detected said correctly distinct outputs.   
     
     
         22 . The memory of  claim 21 , wherein said operation parameters comprise one or more of internal supply voltages, sense amplifier timings, setup timings in data paths, hold timings in data paths, and an ON/OFF state of one or more memory functions. 
     
     
         23 - 24 . (canceled) 
     
     
         25 . A memory comprising:
 at least one phase change memory array;   a test logic configured to read/write test memory elements in said array, and to write redundancy information corresponding to defective memory elements that fail said read/write testing to a table of defective memory locations, said table residing in phase change memory when power is OFF;   a voltage qualification unit configured to test whether reads of multiple phase change memory reference cells produce different outputs corresponding to the different logic states stored in said reference cells, and to allow a redundancy logic to begin redirecting accesses from said defective memory elements to redundant phase change memory elements, in dependence on said table, only after said outputs correspond to said logic states,   wherein said test uses a voltage generated using said power to the memory.   
     
     
         26 . The memory of  claim 25 , further comprising repair logic which applies one or more activation voltage variances to adjust feature activation voltages in said memory, said activation voltage variances being at least partially specified by values residing in a phase change memory when power to the memory is OFF, wherein said voltage qualification unit is configured to allow said repair logic to begin adjusting said feature activation voltages only after said outputs correspond to said logic states. 
     
     
         27 . The memory of  claim 26 , wherein said activation voltage variances correct for differences between designed feature activation voltages and as-manufactured feature activation voltages. 
     
     
         28 . The memory of  claim 25 , wherein said reference cells comprise one or more pairs of reference cells configured to store complementary logic states. 
     
     
         29 . A memory comprising:
 at least one phase change memory array;   a test logic configured to read/write test memory elements in said array, and to write redundancy information corresponding to defective memory elements that fail said read/write testing to a table of defective memory locations, said table residing in phase change memory when power is OFF;   a voltage qualification unit configured to test whether reads of multiple phase change memory reference cells produce different outputs corresponding to the different logic states stored in said reference cells, and to allow a redundancy logic to begin redirecting accesses from said defective memory elements to redundant phase change memory elements, in dependence on said table, only after said outputs correspond to said logic states,   wherein said test uses a voltage generated using said power to the memory;   configuration logic which loads configuration information from a phase change memory into a volatile memory, said configuration information residing in said phase change memory when power to the memory is OFF, said configuration information at least partially determining one or more operation parameters of said memory, wherein said voltage qualification unit is configured to allow said configuration logic to begin loading configuration information only after said outputs correspond to said logic states.   
     
     
         30 . The memory of  claim 29 , wherein said operation parameters comprise one or more of internal supply voltages, sense amplifier timings, setup timings in data paths, hold timings in data paths, and an ON/OFF state of one or more memory functions. 
     
     
         31 . The memory of  claim 25 , wherein different numbers of reference cells store different ones of said different logic states. 
     
     
         32 . The memory of  claim 25 , wherein said testing comprises performing multiple comparisons between said outputs and said logic states, and said corresponding comprises a pre-determined number of uninterrupted matches between said outputs and said logic states. 
     
     
         33 - 64 . (canceled)