Robust Initialization with Phase Change Memory Cells in Both Configuration and Array

Abstract

The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data.

1 .- 32 . (canceled) 
     
     
         33 . A method of accessing a memory comprising:
 redirecting attempted accesses from defective memory elements in an array of phase change memory cells to redundant memory elements using a redundancy logic, said redirecting being performed in dependence on a table of defective memory locations residing in phase change memory when power to the memory is OFF; and   testing, using a voltage qualification unit, whether reads of a plurality of phase change memory reference cells produce different outputs corresponding to the different logic states stored in said reference cells; and   allowing said redundancy logic to begin redirecting accesses only after said outputs correspond to said logic states,   wherein said testing uses a read voltage generated using said power to the memory.   
     
     
         34 . The method of accessing a memory of  claim 33 , further comprising applying one or more activation voltage variances, using a repair logic, to adjust feature activation voltages in said memory, said activation voltage variances being at least partially specified by values residing in a phase change memory when power to the memory is OFF; and allowing said repair logic to begin adjusting said feature activation voltages only after said outputs correspond to said logic states. 
     
     
         35 . The method of accessing a memory of  claim 33 , wherein said activation voltage variances correct for differences between designed feature activation voltages and as-manufactured feature activation voltages. 
     
     
         36 . The method of accessing a memory of  claim 33 , wherein said reference cells comprise one or more pairs of reference cells configured to store complementary logic states. 
     
     
         37 . The method of accessing a memory of  claim 33 , further comprising loading configuration information, using a configuration logic, from a phase change memory into a volatile memory, said configuration information residing in said phase change memory when power to the memory is OFF, said configuration information specifying at least one of a machine execution state or at least one operation parameter of said memory; and allowing said configuration logic to begin loading configuration information only after said outputs correspond to said logic states. 
     
     
         38 . The method of accessing a memory of  claim 37 , wherein said operation parameters comprise one or more of internal supply voltages, sense amplifier timings, setup timings in data paths, hold timings in data paths, and an ON/OFF state of one or more memory functions. 
     
     
         39 . The method of accessing a memory of  claim 33 , wherein different numbers of reference cells store different ones of said different logic states. 
     
     
         40 . The method of accessing a memory of  claim 33 , wherein said testing comprises performing multiple comparisons between said outputs and said logic states, and said corresponding comprises a pre-determined number of uninterrupted matches between said outputs and said logic states. 
     
     
         41 . A method of accessing a memory comprising:
 redirecting attempted accesses from defective memory elements in at least one array of phase change memory cells to redundant memory elements using a redundancy logic, said redirecting being performed in dependence on a table of defective memory locations residing in phase change memory when power to the memory is OFF; and   causing said redundancy logic to begin redirecting accesses, using a voltage qualification unit, only after reads of a plurality of phase change memory reference cells are accurate.   
     
     
         42 . The method of accessing a memory of  claim 41 , further comprising applying one or more activation voltage variances, using a repair logic, to adjust feature activation voltages in said memory, said activation voltage variances being at least partially specified by values residing in a phase change memory when power to the memory is OFF; and only after reads of a plurality of phase change memory reference cells are accurate. 
     
     
         43 . The method of accessing a memory of  claim 42 , wherein said activation voltage variances correct for differences between designed feature activation voltages and as-manufactured feature activation voltages. 
     
     
         44 . The method of accessing a memory of  claim 41 , wherein said reference cells comprise one or more pairs of reference cells configured to store complementary logic states. 
     
     
         45 . The method of accessing a memory of  claim 41 , further comprising loading configuration information, using a configuration logic, from a phase change memory into a volatile memory, said configuration information residing in said phase change memory when power to the memory is OFF, said configuration information specifying at least one of a machine execution state or at least one operation parameter of said memory; and only after reads of a plurality of phase change memory reference cells are accurate. 
     
     
         46 . The method of accessing a memory of  claim 41 , wherein said operation parameters comprise one or more of internal supply voltages, sense amplifier timings, setup timings in data paths, hold timings in data paths, and an ON/OFF state of one or more memory functions. 
     
     
         47 . The method of accessing a memory of  claim 41 , wherein different numbers of reference cells store different ones of said different logic states. 
     
     
         48 .- 64 . (canceled)