Robust Initialization with Phase Change Memory Cells in Both Configuration and Array

Abstract

The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data.

1 .- 48 . (canceled) 
     
     
         49 . A method of accessing a memory comprising:
 controlling access to at least one array of phase change memory cells, using an access logic, said controlling being in at least partial dependence on redundancy data stored in at least one redundancy data storage, said redundancy data storage comprising a plurality of phase change memory cells; and   detecting, using a voltage qualification unit, whether the supply voltage causes reads of a plurality of phase change memory reference cells to produce correctly distinct outputs corresponding to different logic states stored in said reference cells,   enabling said access logic only after said voltage qualification unit has detected said correctly distinct outputs.   
     
     
         50 . The method of accessing a memory of  claim 49 , further comprising applying one or more activation voltage variances, using a repair logic, to adjust feature activation voltages in said memory, said activation voltage variances being at least partially specified by values residing in a phase change memory when power to the memory is OFF; and enabling said repair logic only after said voltage qualification unit has detected said correctly distinct outputs. 
     
     
         51 . The method of accessing a memory of  claim 50 , wherein said activation voltage variances correct for differences between designed feature activation voltages and as-manufactured feature activation voltages. 
     
     
         52 . The method of accessing a memory of  claim 49 , wherein said reference cells comprise one or more pairs of reference cells configured to store complementary logic states. 
     
     
         53 . The method of accessing a memory of  claim 49 , further comprising loading configuration information, using a configuration logic, from a phase change memory into a volatile memory, said configuration information residing in said phase change memory when power to the memory is OFF, said configuration information specifying at least one of a machine execution state or at least one operation parameter of said memory; and enabling said configuration logic only after said voltage qualification unit has detected said correctly distinct outputs. 
     
     
         54 . The method of accessing a memory of  claim 53 , wherein said operation parameters comprise one or more of internal supply voltages, sense amplifier timings, setup timings in data paths, hold timings in data paths, and an ON/OFF state of one or more memory functions. 
     
     
         55 . The method of accessing a memory of  claim 49 , wherein different numbers of reference cells store different ones of said different logic states. 
     
     
         56 . (canceled) 
     
     
         57 . A method of accessing a memory comprising:
 read/write testing memory elements in at least one phase change memory array;   writing redundancy information corresponding to defective memory elements that fail said read/write testing to a table of defective memory locations, said table residing in phase change memory when power to the memory is OFF;   testing whether an input voltage generated using power to the memory causes different read outputs of multiple phase change memory reference cells to correspond to different logic states stored in said reference cells; and   allowing a redundancy logic to begin redirecting accesses from said defective memory elements to redundant phase change memory elements in dependence on said table, only after said read outputs correspond to said logic states.   
     
     
         58 . The method of accessing a memory of  claim 57 , further comprising applying one or more activation voltage variances, using a repair logic, to adjust feature activation voltages in said memory, said activation voltage variances being at least partially specified by values residing in a phase change memory when power to the memory is OFF; and allowing said repair logic to begin adjusting said feature activation voltages only after said outputs correspond to said logic states. 
     
     
         59 . The method of accessing a memory of  claim 58 , wherein said activation voltage variances correct for differences between designed feature activation voltages and as-manufactured feature activation voltages. 
     
     
         60 . The method of accessing a memory of  claim 57 , wherein said reference cells comprise one or more pairs of reference cells configured to store complementary logic states. 
     
     
         61 . The method of accessing a memory of  claim 57 , further comprising loading configuration information, using a configuration logic, from a phase change memory into a volatile memory, said configuration information residing in said phase change memory when power to the memory is OFF, said configuration information specifying at least one of a machine execution state or at least one operation parameter of said memory; and allowing said configuration logic to begin loading configuration information only after said outputs correspond to said logic states. 
     
     
         62 . The method of accessing a memory of  claim 61 , wherein said operation parameters comprise one or more of internal supply voltages, sense amplifier timings, setup timings in data paths, hold timings in data paths, and an ON/OFF state of one or more memory functions. 
     
     
         63 . The method of accessing a memory of  claim 57 , wherein different numbers of reference cells store different ones of said different logic states. 
     
     
         64 . A method of accessing a memory comprising:
 read write testing memo elements in at least one phase change memory array;   writing redundancy information corresponding to defective memory elements that fail said read/write testing to a table of defective memory locations, said table residing in phase change memory when power to the memory is OFF;   testing whether an input voltage generated using power to the memory causes different read outputs of multiple phase change memory reference cells to correspond to different logic states stored in said reference cells; and   allowing a redundancy logic to begin redirecting accesses from said defective memory elements to redundant phase change memory elements in dependence on said table, only after said read outputs correspond to said logic states;   wherein said testing comprises performing multiple comparisons between said outputs and said logic states, and said corresponding comprises a pre-determined number of uninterrupted matches between said outputs and said logic states.