Method and system for a configurable hardware module

Abstract

Provided is a programmable logic system for controlling an external device including a first processor and one or more system input/output (I/O) modules coupled to the processor via an interface. The programmable logic system also includes a configurable hardware module coupled to the processor and the I/O modules via the interface.

What is claimed is: 
     
         1 . A programmable logic system for controlling an external device, comprising:
 a first processor;   one or more system input/output (I/O) modules coupled to the processor via an interface; and   a configurable hardware module coupled to the processor and the I/O modules via the interface.   
     
     
         2 . The programmable logic system of  claim 1 , wherein the system is a programmable logic controller (PLC). 
     
     
         3 . The programmable logic system of  claim 1 , wherein the external device includes a turbine engine. 
     
     
         4 . The programmable logic system of  claim 1 , wherein the first processor includes at least one from the group including a central processing unit (CPU), a graphics processing unit (GPU), and an accelerated processing device (APD). 
     
     
         5 . The programmable logic system of  claim 1 , wherein the configurable hardware module includes a field programmable gate array (FPGA). 
     
     
         6 . The programmable logic system of  claim 1 , wherein the configurable hardware module includes;
 an internal bus coupling the hardware module to the interface,   a field programmable gate array (FPGA) coupled to the bus, and   an external I/O module having one port coupled to the FPGA and another port configured for coupling to the external device.   
     
     
         7 . The programmable logic system of  claim 1 , wherein the configurable hardware module includes;
 an internal bus coupling the hardware module to the interface,   a second processor coupled to the bus, and   an external I/O module having one port coupled to the second processor and another port configured for coupling to the external device.   
     
     
         8 . The programmable logic system of  claim 7 , wherein the second processor includes at least one from the a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a graphics processing unit (GPU), and an accelerated processing device (APD). 
     
     
         9 . Programmable logic system of  claim 7 , wherein at least one of the first and second processors is a multicore processor. 
     
     
         10 . The programmable logic system of  claim 8 , wherein the external I/O module is configurable to facilitate at least one of analog connectivity, digital connectivity, and communications. 
     
     
         11 . Programmable logic system of  claim 10 , wherein the configurable hardware module is configured to provide safety integrity level 3 (SIL-3) functionality. 
     
     
         12 . A configurable hardware module, comprising:
 a bus configured for coupling the hardware module to an external interface;   a processor having a first port coupled to the bus; and   an external input/output (I/O) module having one port coupled to a second port of the processor and another port configured for coupling to an external device.   
     
     
         13 . The configurable hardware module of  claim 12 , wherein the processor includes at least one from the group including a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a graphics processing unit (GPU), and an accelerated processing device (APD). 
     
     
         14 . The configurable hardware module of  claim 12 , wherein the external I/O module is configurable to facilitate at least one of analog connectivity, digital connectivity, and communications. 
     
     
         15 . The configuration hardware module of  claim 14 , wherein the external I/O module is safety integrity level 3 (SIL-3) certified. 
     
     
         16 . A method for controlling operation of a device, comprising:
 creating one or more configuration files related to the operation of the device;   programming configurable logic within a field programmable gate array (FPGA) in accordance with the configuration files; and   controlling the operation of the device with the programmed FPGA via an input output module.   
     
     
         17 . The method of  claim 16 , further comprising using a processor to control the FPGA via a bus interface coupled thereto. 
     
     
         18 . A computer readable medium having stored thereon computer executable instructions that, if executed by a computing device, cause the computing device to perform a method comprising:
 creating one or more configuration files related to the operation of the device;   programming configurable logic within a field programmable gate array (FPGA) in accordance with the configuration files; and   controlling the operation of the device with the programmed FPGA via an input output module.   
     
     
         19 . The computer readable medium of  claim 18 , further comprising using a processor to control the FPGA via a bus interface coupled thereto. 
     
     
         20 . The computer readable medium of claim wherein the method is configured to provide safety integrity level 3 (SIL-3) functionality.