Semiconductor device and method of adjusting characteristic thereof

Abstract

To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

1 .- 17 . (canceled) 
     
     
         18 . A semiconductor device comprising:
 a data output terminal;   a first buffer including a first transistor circuit having transistors of a first conductivity type, wherein the first transistor circuit is disposed between the data output terminal and a first power supply voltage node, and wherein an impedance of the first transistor circuit is controlled by a first adjustment code;   a second buffer that includes a second transistor circuit having transistors of a second conductivity type, wherein the second transistor circuit is disposed between the data output terminal and a second power supply voltage node, and wherein an impedance of the second transistor circuit is controlled by a second adjustment code; and   an output control circuit that generates the first and second adjustment codes, wherein the output control circuit comprises a counter having a counter value that is variable between a maximum value and a minimum value, and wherein the counter value is initialized to a predetermined value between the maximum value and the minimum value when the output control circuit receives a calibration command.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the output control circuit comprises:
 a first replica buffer that includes a third transistor circuit having transistors of the first conductivity type, wherein an impedance of the third transistor circuit is controlled by the first adjustment code;   a second replica buffer that includes a fourth transistor circuit having transistors of the second conductivity type, wherein an impedance of the fourth transistor circuit is controlled by the second adjustment code;   a first comparator that compares an output voltage of the first replica buffer with a first reference voltage; and   a second comparator that compares an output voltage of the second replica buffer with a second reference voltage.   
     
     
         20 . The semiconductor device of  claim 19 , further comprising a calibration terminal, wherein:
 the first replica buffer is connected between the calibration terminal and the first power supply voltage node;   the second replica buffer is connected between an internal contact and the second power supply voltage node;   the output voltage of the first replica buffer is provided to the calibration terminal; and   the output voltage of the second replica buffer is provided to the internal contact.   
     
     
         21 . The semiconductor device of  claim 20 , wherein the output control circuit comprises a third replica buffer including a fifth transistor circuit having transistors of the first conductive type, wherein the fifth transistor circuit is connected between the first power supply and the internal contact, and wherein an impedance of the fifth transistor circuit is controlled by the first adjustment code. 
     
     
         22 . The semiconductor device of  claim 19 , wherein the output control circuit comprises a reference voltage adjustment circuit that adjusts at least one of the first and second reference voltages. 
     
     
         23 . The semiconductor device of  claim 19 , wherein the output control circuit comprises an update clock synchronized with an output from the first comparator and synchronized with an output from the second comparator. 
     
     
         24 . The semiconductor device of  claim 23 , wherein the output control circuit comprises a frequency division circuit configured to divide a frequency of an internal clock to generate the update clock. 
     
     
         25 . The semiconductor device of  claim 18 , wherein the first and second adjustment codes each comprise a plurality of bits. 
     
     
         26 . A semiconductor device comprising:
 a calibration terminal;   a first counter that outputs a first adjustment code, wherein the first counter comprises a first counter value that is variable between a first maximum value and a first minimum value, and wherein the first counter value is initialized to a first predetermined value between the first maximum value and the first minimum value;   a first replica buffer connected between the calibration terminal and a first power supply voltage node, wherein an impedance of the first replica buffer is controlled by the first adjustment code;   a first comparator configured to compare a voltage at the calibration terminal with a first reference voltage; and   a counter control circuit that determines a logic level of the first comparator in synchronization with an update clock, wherein the counter control circuit is configured to update the first adjustment code retained in the first counter based on the determined logic level of the first comparator.   
     
     
         27 . The semiconductor device of  claim 26 , further comprising:
 a second counter that outputs a second adjustment code, wherein the second counter comprises a second counter value that is variable between a second maximum value and a second minimum value, and wherein the second counter value is initialized to a second predetermined value between the second maximum value and the second minimum value;   a second replica buffer connected between an internal contact and a second power supply voltage node, wherein an impedance of the second replica buffer is controlled by the second adjustment code; and   a second comparator configured to compare a voltage at the internal contact with a second reference voltage;   wherein the counter control circuit determines a logic level of the second comparator in synchronization with the update clock, and wherein the counter control circuit is configured to update the second adjustment code retained in the second counter based on the determined logic level of the second comparator.   
     
     
         28 . The semiconductor device of  claim 27 , further comprising a third replica buffer connected between the first power supply voltage node and the internal contact, wherein an impedance of the third replica buffer is the same as the impedance of the first replica buffer. 
     
     
         29 . The semiconductor device of  claim 26 , further comprising a frequency division circuit configured to divide a frequency of an internal clock to generate the update clock. 
     
     
         30 . The semiconductor device of  claim 26 , wherein the first adjustment code comprises a plurality of bits. 
     
     
         31 . A semiconductor device comprising:
 an output buffer;   a calibration terminal configured to be coupled to an external resistor; and   a control circuit coupled to the output buffer and the calibration terminal, wherein the control circuit is configured to control an output impedance of the output buffer in response to the external resistor, and wherein the control circuit comprises a counter, the output impedance of the output buffer is dependent on a counter value of the counter, the counter value of the counter is variable between a first maximum value and a first minimum value, and the counter value of the counter is initialized to a first predetermined value between the first maximum value and the first minimum value when the control circuit receives a calibration command.   
     
     
         32 . The semiconductor device of  claim 31 , wherein the control circuit comprises:
 a replica buffer coupled to the calibration terminal through a first node; and   a comparator configured to compare a voltage at the first node with a reference voltage at a second node to produce a control signal.   
     
     
         33 . The semiconductor device of  claim 31 , wherein the output buffer includes a first conductive type transistor and a second conductive type transistor, wherein an output impedance of the first conductive type transistor is dependent on the counter value of the counter. 
     
     
         34 . The semiconductor device of  claim 33 , wherein the control circuit comprises an additional counter, an output impedance of the second conductive type transistor is dependent on a counter value of the additional counter. 
     
     
         35 . The semiconductor device of  claim 34 , wherein the counter value of the additional counter is variable between a second maximum value and a second minimum value, and the counter value of the additional counter is initialized to a second predetermined value between the second maximum value and the second minimum value when the control circuit receives the calibration command. 
     
     
         36 . The semiconductor device of  claim 31 , wherein the control circuit is configured to control the output impedance of the output buffer by providing an adjustment code to the output buffer. 
     
     
         37 . The semiconductor device of  claim 36 , wherein the adjustment code is generated based on the counter value of the counter.