Synchronized multiple imager system and method

Abstract

One embodiment relates to a synchronized multiple imager system includes a plurality of imagers. One or more respective sensors are coupled to the imagers. The sensors output a vertical raster stream representative of pixel data from pixel columns, thereby generating a plurality of vertical raster streams. A clock circuit synchronizes the sensors to sense selected columns in the imagers and to output the vertical raster streams from the selected columns. A processor circuit stitches seam vertical raster streams from adjacent pairs of imagers. The synchronized multiple imager system may further include a plurality of input buffers coupled to respective sensors. The clock circuit may include flip-flops configured to acquire the vertical raster stream from respective imagers in accordance with an integer bus clock. The clock circuit may further include asynchronous FIFOs to de-skew the vertical raster streams. Other embodiments, aspects and features are disclosed.

What is claimed is: 
     
         1 . A synchronized multiple imager system, comprising:
 a plurality of imagers having pixels arranged in multiple rows and columns; the pixels operable to generate pixel data responsive to light directed onto the imagers;   one or more respective sensors coupled to the imagers, the sensors operable to sense the pixel data from the columns and output vertical raster streams representative of the pixel data in the columns;   a clock circuit coupled to the imagers and operable to synchronize the sensors to sense selected columns in the imagers and to output the vertical raster streams from the selected columns; and   a processor circuit configured to receive the vertical raster streams from the imagers and operable to process the vertical raster streams to generate a plurality of stitched raster streams.   
     
     
         2 . The synchronized multiple imager system of  claim 1 , wherein the processor circuit processes seam vertical raster streams from adjacent pairs of imagers. 
     
     
         3 . The synchronized multiple imager system of  claim 1 , further comprising one or more input buffers coupled to a respective sensor, the input buffers configured to receive the vertical raster streams and forward the vertical raster streams to the processor circuit. 
     
     
         4 . The synchronized multiple imager system of  claim 1 , wherein the pixel data in the imager is sensed on a column by column basis, and wherein the vertical raster stream from the column is loaded into the input buffer. 
     
     
         5 . The synchronized multiple imager system of  claim 1 , wherein the vertical raster streams are de-warped by the processor circuit. 
     
     
         6 . The synchronized multiple imager system of  claim 1 , wherein the seam vertical raster streams are generated from the seam columns. 
     
     
         7 . The synchronized multiple imager system of  claim 1 , wherein the clock circuit includes input flip-flops configured to acquire the vertical raster stream from a respective imager. 
     
     
         8 . The synchronized multiple imager system of  claim 1 , wherein the clock circuit includes asynchronous FIFOs coupled to the input flip-flops, the asynchronous FIFO operable to de-skew the vertical raster streams. 
     
     
         9 . The synchronized multiple imager system of  claim 1 , wherein the clock circuit includes a write FIFO configured to receive the vertical raster streams from the asynchronous FIFOs and operable to output synchronized vertical raster streams. 
     
     
         10 . The synchronized multiple imager system of  claim 1 , wherein the system is implemented in a programmable hardware. 
     
     
         11 . The synchronized multiple imager system of  claim 1 , wherein the system is implemented in an ASIC. 
     
     
         12 . A synchronized multiple imager system, comprising:
 a plurality of imagers configured to acquire a segment of an image, the imagers having pixels arranged in multiple rows and columns, the pixels operable to generate pixel data responsive to the segment acquired by the respective imager;   one or more respective sensors coupled to the imagers, the sensors operable to sense the pixel data from the columns and output a vertical raster stream representative of the pixel data,;   a clock circuit coupled to the imagers and operable to synchronize the sensors to sense selected columns in the imagers and to output the vertical raster streams from the selected columns; and   a processor circuit configured to receive one or more vertical raster streams from the imagers and operable to process the vertical raster streams to generate a plurality of stitched raster streams.   
     
     
         13 . The synchronized multiple imager system of  claim 12 , wherein the processor circuit processes seam vertical raster streams from adjacent pairs of imagers. 
     
     
         14 . The synchronized multiple imager system of  claim 12 , further comprising a plurality of input buffers coupled to a respective sensor, the input buffers configured to receive the vertical raster streams and forward the vertical raster streams to the processor circuit. 
     
     
         15 . The synchronized multiple imager system of  claim 12 , wherein the pixel data in the imager is sensed on a column by column basis, and wherein the vertical raster stream from the columns are loaded into the input buffer. 
     
     
         16 . The synchronized multiple imager system of  claim 12 , wherein the vertical raster streams are de-warped by the processor circuit. 
     
     
         17 . The synchronized multiple imager system of  claim 12 , wherein the seam vertical raster streams are generated from the seam columns. 
     
     
         18 . The synchronized multiple imager system of  claim 12 , wherein the clock circuit includes input flip-flops each configured to acquire the vertical raster stream from a respective imager in accordance with an imager bus clock. 
     
     
         19 . The synchronized multiple imager system of  claim 12 , wherein the clock circuit includes asynchronous FIFOs coupled to the input flip-flops, the asynchronous FIFO operable to de-skew the vertical raster streams. 
     
     
         20 . The synchronized multiple imager system of  claim 12 , wherein the clock circuit includes a write FIFO configured to receive the vertical raster streams from the asynchronous FIFOs and operable to output synchronized vertical raster streams.