Through substrate via (tsuv) structures and method of making the same

Abstract

Through substrate via (TSuV) structures and method of making the same are disclosed herein. In embodiments, TSuV structures are metal filled selectively to avoid forming significant metal overburden on non-via surfaces of the substrate. In certain embodiments, post-fill metal removal/planarization operations are eliminated for reduced process complexity and manufacturing cost. In embodiments, selective metal fill entails selective electroless or electrolytic deposition. Both front side and back side selective deposition methods are described along with features of through substrate via structures made with such methods.

What is claimed is: 
     
         1 . A microelectronic device, comprising:
 a substrate;   a through substrate via (TSuV) extending through the substrate;   a dielectric liner disposed over a sidewall of the TSuV and substrate surface; and   a via metal disposed in the via, wherein the via metal is in direct contact with the dielectric liner, and wherein the via metal is of homogenous composition across the diameter of the TSuV.   
     
     
         2 . The microelectronic device of  claim 1 , wherein the metal comprises copper (Cu) with less than 1 PPM of any of: hydrogen (H), chlorine (Cl), oxygen (O), sulfur (S), carbon (C), or nitrogen (N). 
     
     
         3 . The microelectronic device of  claim 1 , wherein the metal is microstructurally homogeneous across the diameter of the TSuV. 
     
     
         4 . The microelectronic device of  claim 1 , wherein the metal further comprises at least one alloy metal selected from the group consisting of: manganese (Mn), tungsten (W), or molybdenum (Mo), magnium (Mg), renium (Re), zirconium (Zr), hafnium (Hf), niobium (Nb), vanadium (V), or titanium (Ti). 
     
     
         5 . The microelectronic device of  claim 1 , wherein the dielectric liner is selected from the group consisting of: silicon dioxide (SiO 2 ), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), silicon nitride (SixNy), silicon carbide (SiC), silicon oxy-carbo-nitride (SiOCN), a benzocyclobutene (BCB)-based polymer, or a (p-xylylene)-based polymer. 
     
     
         6 . The microelectronic device of  claim 5 , wherein the dielectric liner comprises at least one of silicon nitride, silicon carbide, silicon oxy-carbo-nitride, or a (p-xylylene)-based polymer. 
     
     
         7 . The microelectronic device of  claim 5 , wherein the metal consists essentially of copper (Cu). 
     
     
         8 . The microelectronic device of  claim 1 , wherein the TSuV extends between a first bump disposed over a first dielectric layer disposed on a front side of the substrate and a second bump disposed over a second dielectric layer disposed on a back side of the substrate. 
     
     
         9 . The microelectronic device of  claim 1 , wherein the TSuV extends between bump disposed over a dielectric layer disposed over a front side of the substrate to a second bump disposed over a back side of the substrate. 
     
     
         10 . The microelectronic device of  claim 1 , wherein the substrate has bumps on both a front side and a back side, and wherein the device further comprises a front side metal pad disposed over a front side of the substrate with a dielectric layer disposed between the front side bump and the front side metal pad, and wherein the TSuV extends between the front side metal pad and the back side bump. 
     
     
         11 . A microelectronic device assembly comprising:
 a first of the microelectronic device in  claim 1 , wherein at least one first metal bump is disposed on a surface of a first TSuV; and   a second of the microelectronic device in  claim 1 , wherein at least one second metal bump is disposed on a surface of a second TSuV, and wherein the first and second TSuVs are stacked together with the first and second metal bumps bonded together.   
     
     
         12 . A microelectronic device assembly comprising:
 a first of the microelectronic device in  claim 1  comprising a first TSuV; and   a second of the microelectronic device in  claim 1  comprising a second TSuV, wherein a first metal bump is disposed on a surface of the first TSuV, and wherein the first and second TSuVs are stacked together with the first metal bump bonded directly to the second TSuV.   
     
     
         13 . The microelectronic device assembly of  claim 12 , wherein the second TSuV is partially filled, with the via metal recessed from a surface of the substrate and the first metal bump disposed in the recess. 
     
     
         14 . The microelectronic device assembly of  claim 13 , wherein the via metal partially filling the second TSuV comprises a surface finish metal distinct from the metal of the first metal bump.