US2014239161A1PendingUtilityA1

Pixel Array With Global Shutter

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Assignee: CMOSIS NVPriority: Apr 7, 2008Filed: May 2, 2014Published: Aug 28, 2014
Est. expiryApr 7, 2028(~1.7 yrs left)· nominal 20-yr term from priority
H04N 25/59H04N 25/65H04N 25/771H04N 25/616H04N 25/532H10F 39/8037H04N 25/78H04N 25/77H04N 25/707H01L 27/14612
58
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Claims

Abstract

A pixel comprises a pinned photodiode for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the pinned photodiode and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage.

Claims

exact text as granted — not AI-modified
1 . A pixel comprising:
 a pinned photodiode for generating charges in response to incident radiation;   a sense node;   a transfer gate, connected between the pinned photodiode and the sense node, for controlling transfer of charges to the sense node;   a reset switch connected to the sense node for resetting the sense node to a predetermined voltage;   a first buffer amplifier having an input connected to the sense node;   a sample stage, connected to an output of the first buffer amplifier, which is operable to sample a value of the sense node; and,   a second buffer amplifier having an input connected to the sample stage.   
     
     
         2 . A pixel according to  claim 1  wherein the sample stage comprises:
 a sample switch connected to an output of the first buffer amplifier; and, 
 a storage element for storing a signal level sampled by the sample switch. 
 
     
     
         3 . A pixel according to  claim 1  further comprising a discharge switch for resetting the sample stage. 
     
     
         4 . A pixel according to  claim 1  wherein the first buffer amplifier is connected to a first control line which is operable to discharge the sample stage. 
     
     
         5 . A pixel according to  claim 4  wherein the reset switch is also connected to the first control line. 
     
     
         6 . A pixel according to  claim 1  further comprising a read switch connected to the output of the second buffer amplifier for reading a signal from the pixel. 
     
     
         7 . A pixel according to  claim 4  wherein the sample stage comprises a sample switch connected to a first node and a storage element connected in series with the sample switch and wherein both of the input to the second buffer amplifier and the output of the first buffer amplifier are connected to the first node. 
     
     
         8 . A pixel according to  claim 1  and control circuitry which is arranged to:
 operate the reset switch to reset the sense node; 
 operate the transfer gate of the pixel to transfer charge from the pinned photodiode to the sense node following exposure to radiation; 
 cause the sample stage of the pixel to sample the signal on the sense node, which sampled signal represents an exposure level of the pixel. 
 
     
     
         9 . A pixel according to  claim 8  wherein the control circuitry is further arranged to:
 read the sampled exposure level of the pixel; 
 
       and subsequently, to:
 cause the sample stage to sample the sense node after it has been reset, which sampled signal represents a reset level of the pixel; and, 
 read the sampled reset level of the pixel. 
 
     
     
         10 . A pixel according to  claim 8  wherein the control circuitry is arranged to operate the reset switch of the pixel while the pinned photodiode of the pixel is being exposed to radiation. 
     
     
         11 . A pixel according to  claim 10  wherein the control circuitry is arranged to operate the reset switch at all times other than when it is required to transfer charge to the sense node and sample a value of the sense node. 
     
     
         12 . A pixel according to  claim 1  and control circuitry which is arranged to:
 reset the sense node; 
 cause the sample stage to sample a signal on the sense node which represents a reset level of the pixel; 
 operate the transfer gate to transfer charge from the pinned photodiode to the sense node following exposure to radiation, which transferred charge represents an exposure level of the pixel; 
 read the sampled reset level of the pixel; 
 cause the sample stage to sample a signal on the sense node which represents an exposure level of the pixel; and, 
 read the sampled exposure level of the pixel. 
 
     
     
         13 . A pixel array comprising an array of pixels according to  claim 1 . 
     
     
         14 . A pixel array according to claim  19  and control circuitry which is arranged to cause the array of pixels to be exposed synchronously. 
     
     
         15 . A pixel array according to claim  19  and wherein the control circuitry is arranged to read a value stored in the sample stage of a pixel in the array for a first exposure period while the pinned photodiode of the pixel is exposed for a second exposure period. 
     
     
         16 . A pixel comprising
 a photo-sensitive element for generating charges in response to incident radiation;   a sense node;   a transfer gate, connected between the photo-sensitive element and the sense node, for controlling transfer of charges to the sense node;   a reset switch connected to the sense node for resetting the sense node to a predetermined voltage;   a first buffer amplifier having an input connected to the sense node;   a first sample stage, connected to an output of the first buffer amplifier, which is operable to sample a reset level of the sense node;   a second sample stage connected to an output of the first buffer amplifier which is operable to sample a value of the sense node;   a second buffer amplifier having an input connected to an output of the first or second sample stages.

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