Semiconductor memory device, method of testing the same and method of operating the same

Abstract

A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

What is claimed is: 
     
         1 . A method of testing a semiconductor memory device, the method comprising:
 writing data to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device;   applying a first driving voltage to a first group of word lines and a second driving voltage to a second group of word lines, wherein each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines and the first driving voltage has a voltage level different from that of the second driving voltage; and   reading the data from first memory cells coupled to the first group of the word lines to determine whether each of the first memory cells is defective.   
     
     
         2 . The method of  claim 1 , wherein the first driving voltage includes a first boosted voltage, and the second driving voltage includes a second boosted voltage. 
     
     
         3 . The method of  claim 2 , wherein the first boosted voltage is higher than the second boosted voltage. 
     
     
         4 . The method of  claim 1 , wherein the first driving voltage includes a second boosted voltage, and the second driving voltage includes a first boosted voltage. 
     
     
         5 . The method of  claim 4 , wherein the first boosted voltage is higher than the second boosted voltage. 
     
     
         6 . The method of  claim 1 , wherein the first driving voltage includes a first negative voltage, and the second driving voltage includes a second negative voltage. 
     
     
         7 . The method of  claim 6 , wherein the first negative voltage is lower than the second negative voltage. 
     
     
         8 . The method of  claim 1 , wherein the first driving voltage includes a second negative voltage, and the second driving voltage includes a first negative voltage. 
     
     
         9 . The method of  claim 8 , wherein the first negative voltage is lower than the second negative voltage. 
     
     
         10 . The method of  claim 1 , wherein writing the data to the plurality of memory cells comprises:
 writing a first data having a logic high level to the first memory cells coupled to the first group of the word lines; and   writing a second data having a logic low level to second memory cells coupled to the second group of the word lines.   
     
     
         11 . The method of  claim 1 , wherein the first group of the word lines include odd-numbered word lines, and the second group of the word lines include even-numbered word lines, wherein each of the first group of the word lines and each of the first group of the word lines are alternately arranged in the memory cell block. 
     
     
         12 . The method of  claim 1 , wherein the testing of the semiconductor memory device is performed at a wafer level in a manufacturing process of the semiconductor memory device. 
     
     
         13 . A method of testing a semiconductor memory device, the method comprising:
 writing data to a plurality of memory cells disposed in the semiconductor memory device, wherein the plurality of the memory cells is coupled to a plurality of word lines;   disabling a first word line of the plurality of the memory cells;   alternately enabling and disabling at least two second word lines while the first word line is disabled, wherein the first word line is interposed between the at least two second word lines; and   reading data from memory cells coupled to the first word line to screen defective memory cells.   
     
     
         14 . The method of  claim 13 , wherein writing the data to the plurality of memory cells comprises:
 writing a first data having a logic high level to first memory cells of the plurality of the memory cells, wherein the first memory cells are coupled to first group of word lines of the plurality of the word lines; and   writing a second data having a logic low level to second memory cells of the plurality of the memory cells, wherein the second memory cells are coupled to second group of the word lines of the plurality of the word lines,   wherein each word line of the first group of the word lines and each word line of the second group of the word lines are alternately arranged in the semiconductor memory device.   
     
     
         15 . The method of  claim 13 , wherein a first voltage is applied to the at least two second word lines when the at least two second word lines are disabled, a second voltage is applied to the first word line when the first word line is disabled, and wherein the first voltage is lower than the second voltage. 
     
     
         16 . A method of operating a semiconductor memory device, the method comprising:
 precharging a plurality of word lines with a first negative voltage;   selecting a first word line of the plurality of the word lines in response to an active command;   applying a second negative voltage to at least one second word line adjacent to the first word line, wherein the first negative voltage has a voltage level different from that of the second negative voltage; and   writing data to memory cells coupled to the first word line.   
     
     
         17 . The method of  claim 16 , wherein the first negative voltage is lower than the second negative voltage. 
     
     
         18 . A semiconductor memory device, comprising:
 a memory cell block configured to include a plurality of memory cells coupled to a plurality of word lines;   a boosted voltage generator configured to generate a first boosted voltage and a second boosted voltage, wherein the first boosted voltage has a voltage level different from that of the second boosted voltage;   a negative voltage generator configured to generate a first negative voltage and a second negative voltage, wherein the first negative voltage has a voltage different from that of the second negative voltage;   a plurality of sub word line drivers, wherein each sub word line driver drives each word line; and   a plurality of switching units, wherein each switching unit is configured to selectively provide one of the first boosted voltage, the second boosted voltage, the first negative voltage and the second negative voltage to a corresponding sub word line driver of the plurality of the sub word line drivers according to an operation mode.   
     
     
         19 . The semiconductor memory device of  claim 18 , wherein when the operation mode corresponds to a first test mode, a first group of the plurality of the sub word line drivers supplies the first boosted voltage to a first group of word lines of the plurality of the word lines, a second group of the plurality of the sub word line drivers supplies the second boosted voltage to a second group of word lines of the plurality of the word lines, and each word line of the first group of the word lines and each word line of the second group of the word lines are alternately arranged in the memory cell block. 
     
     
         20 . The semiconductor memory device of  claim 19 , wherein the second boosted voltage is lower than the first boosted voltage. 
     
     
         21 . The semiconductor memory device of  claim 18 , wherein when the operation mode corresponds to a second test mode, a first group of the plurality of the sub word line drivers supplies the first negative voltage to a first group of word lines of the plurality of the word lines, a second group of the plurality of the sub word line drivers supplies the second negative voltage to a second group of word lines of the plurality of the word lines, and each word line of the first group of the word lines and each word line of the second group the word lines are alternately arranged in the memory cell block. 
     
     
         22 . The semiconductor memory device of  claim 21 , wherein the second negative voltage is higher than the first negative voltage. 
     
     
         23 . The semiconductor memory device of  claim 18 , wherein when the operation mode corresponds to perform a writing operation on first memory cells, a first sub word line driver drives the first boosted voltage to a first word line coupled to the first memory cells, at least one second sub word line driver drives the second negative voltage to at least one neighboring word line adjacent to the first word line. 
     
     
         24 . The semiconductor memory device of  claim 23 , wherein remaining sub word line drivers other than the first sub word line driver and the at least one second sub word line driver drive the first negative voltage to remaining word lines except the first sub word line and the at least one neighboring word line during the write operation on the first memory cells. 
     
     
         25 . The semiconductor memory device of  claim 23 , wherein the first negative voltage is lower than the second negative voltage. 
     
     
         26 . A semiconductor memory device, comprising:
 a mode control unit configured to generate a plurality of selection signals in response to a plurality of test signals;   a boosted voltage generator configured to generate a first boosted voltage and a second boosted voltage, wherein the first boosted voltage has a voltage level different from that of the second boosted voltage;   a negative voltage generator configured to generate a first negative voltage and a second negative voltage, wherein the first negative voltage has a voltage different from that of the second negative voltage;   a sub word line driver configured to provide a driving voltage to a word line; and   a switching unit configured to selectively provide one of the first boosted voltage, the second boosted voltage, the first negative voltage and the second negative voltage to the sub word line driver according to the plurality of the selection signals.