Method of fabricating semiconductor package

Abstract

A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor package, the method comprising:
 providing a wafer which comprises an upper area having through silicon vias (TSVs) and a lower area not having the TSVs;   mounting a semiconductor chip on the upper area of the wafer;   forming a passivation layer to a predetermined thickness to cover the semiconductor chip;   exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and   exposing a top surface of the semiconductor chip by partially removing the passivation layer.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming connection terminals, which are electrically connected to the exposed TSVs, on a bottom surface of the wafer before the exposing of the top surface of the semiconductor chip by partially removing the passivation layer.   
     
     
         3 . The method of  claim 2 , wherein the connection terminals comprise bottom pads and bump balls. 
     
     
         4 . The method of  claim 2 , wherein the connection terminals are protected with a protective tape when the top surface of the semiconductor chip is exposed by partially removing the passivation layer. 
     
     
         5 . The method of  claim 2 , further comprising, after the exposing of the top surface of the semiconductor chip,:
 forming sub-packages by sawing the wafer into a plurality of unit wafers; and   mounting the sub-packages on a printed circuit board (PCB).   
     
     
         6 . The method of  claim 5 , further comprising:
 forming semiconductor packages by sawing the PCB after the mounting of the sub-packages on the PCB.   
     
     
         7 . The method of  claim 1 , wherein the mounting of the semiconductor chip comprises mounting the semiconductor chip in the form of a flip-chip. 
     
     
         8 . The method of  claim 7 , wherein the wafer further comprises top pads which are electrically connected to the semiconductor chip and a redistribution layer which electrically connects the TSVs and the top pads through redistribution lines included therein. 
     
     
         9 . The method of  claim 1 , wherein the wafer comprises a plurality of unit wafers, wherein each of the unit wafers is wider than the semiconductor chip. 
     
     
         10 . The method of  claim 1 , wherein the wafer comprises a plurality of unit wafers, wherein each of the unit wafers is narrower than the semiconductor chip. 
     
     
         11 . The method of  claim 10 , further comprising forming through vias which penetrate the passivation layer and are electrically connected to the semiconductor chip. 
     
     
         12 . A method of fabricating a semiconductor package, the method comprising:
 providing a wafer which comprises an upper area having TSVs and a lower area not having the TSVs;   mounting a semiconductor chip on the upper area of the wafer;   forming a passivation layer to a predetermined thickness to cover the semiconductor chip;   exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer;   forming bottom pads and bump balls, which are electrically connected to the exposed TSVs, on a bottom surface of the wafer; and   exposing a top surface of the semiconductor chip by partially removing the passivation layer.   
     
     
         13 . The method of  claim 12 , wherein the exposing of the TSVs by removing the lower area of the wafer comprises exposing the TSVs by removing the lower area of the wafer in the state where no support is attached to the wafer. 
     
     
         14 . The method of  claim 12 , wherein the wafer further comprises top pads which are arranged at a first interval and a redistribution layer which electrically connects the TSVs and the top pads through redistribution lines included therein, and the TSVs are arranged at a second interval different from the first interval. 
     
     
         15 . The method of  claim 14 , wherein the first interval is smaller than the second interval. 
     
     
         16 . A method of fabricating a semiconductor package, the method comprising:
 providing a wafer which comprises a first area having through silicon vias (TSVs) and a second area not having the TSVs;   mounting a semiconductor chip on the first area of the wafer, the semiconductor chip being wider than the wafer to extend beyond sides thereof;   forming a passivation layer to a predetermined thickness to cover the wafer and exposed portions of the semiconductor chip extending beyond the wafer; and   exposing the TSVs by removing the second area of the wafer and corresponding portion of the passivation layer in a state where no support is attached to the wafer.   
     
     
         17 . The method of  claim 16 , further comprising:
 forming through vias in the remaining passivation layer to be electrically connected to power/ground pads of the semiconductor chip when the through vias in the first area are being exposed.   
     
     
         18 . The method of  claim 17 , further comprising:
 forming connection terminals to be electrically connected to the exposed TSVs on a bottom surface of the wafer; and   forming connection terminals to be electrically connected to the exposed through vias of the passivation layer.   
     
     
         19 . The method of  claim 16 , wherein the mounting of the semiconductor chip comprises mounting the semiconductor chip in the form of a flip-chip. 
     
     
         20 . The method of  claim 19 , wherein the wafer comprises:
 top pads which are electrically connected to the semiconductor chip; and   a redistribution layer which electrically connects the TSVs and the top pads through redistribution lines included therein.