Method for fabricating nonvolatile memory structure

Abstract

A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.

What is claimed is: 
     
         1 . A method for forming a nonvolatile memory, comprising:
 forming an oxide define region in a semiconductor substrate of a first conductivity type, wherein the oxide define region is encompassed by at least a first isolation region and a second isolation region;   forming a first doping region of a second conductivity type in the semiconductor substrate;   forming a second doping region of a third conductivity type in the first doping region, wherein the second doping region partially overlaps with the oxide define region, and wherein the second doping region encompasses the first isolation region;   forming a third doping region of the third conductivity type in the first doping region, wherein the third doping region partially overlaps with the oxide define region, and wherein the third doping region encompasses the second isolation region;   forming a gate dielectric layer on the oxide define region;   forming a gate material layer on the gate dielectric layer; and   etching the gate material layer to form a gate pattern wherein the gate pattern has one edge situated directly on the first isolation region and an opposite second edge situated directly on the second isolation region.   
     
     
         2 . The method for forming a nonvolatile memory according to  claim 1  wherein the gate material layer comprises polysilicon. 
     
     
         3 . The method for forming a nonvolatile memory according to  claim 1  wherein the first conductivity type is P type and the second conductivity type is P type, and the third conductivity type is N type. 
     
     
         4 . The method for forming a nonvolatile memory according to  claim 1  wherein the first conductivity type is P type, the second conductivity type is N type, and the third conductivity type is P type. 
     
     
         5 . The method for forming a nonvolatile memory according to  claim 4  further comprising forming a deep doping region underneath the first doping region. 
     
     
         6 . The method for forming a nonvolatile memory according to  claim 5  wherein the deep doping region is N type. 
     
     
         7 . A method for forming a nonvolatile memory, comprising:
 forming an oxide define region in a semiconductor substrate of a first conductivity type, wherein the oxide define region is encompassed by at least a first isolation region and a second isolation region;   forming a first doping region of a second conductivity type in the semiconductor substrate;   forming a second doping region of a third conductivity type in the first doping region, wherein the second doping region partially overlaps with the oxide define region, and wherein the second doping region encompasses the first isolation region;   forming a third doping region of the third conductivity type in the first doping region, wherein the third doping region partially overlaps with the oxide define region, and wherein the third doping region encompasses the second isolation region;   forming a gate dielectric layer on the oxide define region;   forming a gate material layer on the gate dielectric layer; and   etching the gate material layer to form a gate pattern wherein the gate pattern has edges apart from the oxide define region.   
     
     
         8 . The method for forming a nonvolatile memory according to  claim 7  wherein the gate material layer comprises polysilicon. 
     
     
         9 . The method for forming a nonvolatile memory according to  claim 7  wherein the first conductivity type is P type and the second conductivity type is P type, and the third conductivity type is N type. 
     
     
         10 . The method for forming a nonvolatile memory according to  claim 7  wherein the first conductivity type is P type, the second conductivity type is N type, and the third conductivity type is P type. 
     
     
         11 . The method for forming a nonvolatile memory according to  claim 10  further comprising forming a deep doping region underneath the first doping region. 
     
     
         12 . The method for forming a nonvolatile memory according to  claim 11  wherein the deep doping region is N type.