Semiconductor Device

Abstract

A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.

What is claimed is: 
     
         1 . A method comprising:
 receiving a first command signal and a clock signal at a first chip;   generating, at a timing control circuit of the first chip, a plurality of second command signals in response to the first command signal and the clock signal, where the plurality of second command signals have different timings from each other in synchronization with the clock signal;   transferring the plurality of second command signals to a corresponding plurality of internal circuits on one or more second chips stacked on the first chip; and   performing at each of the plurality of internal circuits an operation indicated by the first command signal in synchronization with a corresponding one of the second command signals.   
     
     
         2 . The method of  claim 1 , wherein the clock signal is not supplied from the first chip to the one or more second chips. 
     
     
         3 . The method of  claim 1 , where transferring the plurality of second command signals comprises transferring the plurality of second command signals through a plurality of first through silicon vias penetrating the first chip and through a plurality of second through silicon vias penetrating the one or more second chips to the corresponding plurality of internal circuits on the one or more second chips. 
     
     
         4 . The method of  claim 1 , where performing at each of the plurality of internal circuits the operation indicated by the first command signal comprises activating a column switch and a data amplifier at each of the plurality of internal circuits in synchronization with a corresponding one of the second command signals, where the column switch at each internal circuit connects a memory cell array and a data bus at the one or more second chips based on an address signal, and where the data amplifier at each internal circuit amplifies data on the corresponding data bus. 
     
     
         5 . The method of  claim 4 , where performing at each of the plurality of internal circuits the operation indicated by the first command signal comprises performing a pre-charge operation at the memory cell array of the one or more second chips in synchronization with one of the second command signals. 
     
     
         6 . The method of  claim 1 , where transferring the plurality of second command signals comprises transferring the plurality of second command signals to a plurality of second chips by commonly supplying the plurality of second command signals and a first chip address to the plurality of second chips, where the first chip address identifies one of the plurality of second chips to the plurality of second chips in synchronization with each of the second command signals. 
     
     
         7 . The method of  claim 6 , where performing at each of the plurality of internal circuits the operation indicated by the first command signal comprises activating an internal circuit when the first chip address matches a second chip address assigned to each of the plurality of second chips. 
     
     
         8 . The method  claim 1 , further comprising outputting read data from a FIFO circuit at the first chip, where the read data is supplied from the one or more second chips in response to at least one of the plurality of second command signals.