Vertical memory devices with vertical isolation structures and methods of fabricating the same

Abstract

A vertical memory device includes a substrate, a column of vertical channels on the substrate and spaced apart along a direction parallel to the substrate, respective charge storage structures on sidewalls of respective ones of the vertical channels and gate electrodes vertically spaced along the charge storage structures. The vertical memory device further includes an isolation pattern disposed adjacent the column of vertical channels and including vertical extension portions extending parallel to the vertical channels and connection portions extending between adjacent ones of the vertical extension portions.

What is claimed is: 
     
         1 . A vertical memory device, comprising:
 a substrate;   a column of vertical channels on the substrate and spaced apart along a first direction parallel to the substrate;   respective charge storage structures on sidewalls of respective ones of the vertical channels;   gate electrodes vertically spaced along the charge storage structures; and   an isolation pattern disposed adjacent the column of vertical channels and including vertical extension portions extending parallel to the vertical channels and connection portions extending between adjacent ones of the vertical extension portions.   
     
     
         2 . The vertical memory device of  claim 1 , wherein the gate electrodes include a ground selection line, a word line and a string selection line vertically spaced apart along the vertical channels, and wherein the connection portions have bottom surfaces disposed between the string selection line and the word line. 
     
     
         3 . The vertical memory device of  claim 2 , wherein the bottom surfaces of the connection portions are disposed lower than a bottom surface of the string selection line and wherein top surfaces of the connection portions are disposed higher than a top surface of the string selection line. 
     
     
         4 . The vertical memory device of  claim 2 , wherein the string selection line comprises string selection lines separated from each other along a second direction parallel to the substrate by the isolation pattern. 
     
     
         5 . The vertical memory device of  claim 1 , wherein the vertical extension portions comprise pillars having a diameter substantially same as an outer diameter of the charge storage structures, and wherein the vertical extension portions have a height substantially same as a height of the charge storage structures. 
     
     
         6 . The vertical memory device of  claim 1 , further comprising respective conductive pads disposed on the vertical channels and the isolation pattern. 
     
     
         7 . The vertical memory device of  claim 6 , wherein the gate electrodes include a ground selection line, a word line and a string selection line vertically spaced apart along the vertical channels, and wherein bottom surfaces of the conductive pads are substantially higher than a top surface of the string selection line. 
     
     
         8 . The vertical memory device of  claim 1 , further comprising respective semiconductor patterns disposed between the vertical extension portions and the substrate and between the charge storage structures and the substrate. 
     
     
         9 . The vertical memory device of  claim 1 , wherein the vertical extension portions and the connection portions consist essentially of an insulating material. 
     
     
         10 . The vertical memory device of  claim 1 , wherein the vertical extension portions comprise charge storage structures. 
     
     
         11 . A vertical memory device, comprising:
 a substrate;   adjacent first and second columns of vertical channels, the vertical channels in each of the first and second columns spaced apart along a first direction parallel to the substrate;   respective charge storage structures on sidewalls of the vertical channels of the first and second columns of vertical channels;   gate electrodes vertically spaced along sidewalls of the charge storage structures;   a wiring extending along the first direction on and electrically connected to a vertical channel of the first column of vertical channels; and   a bit line extending in a second direction substantially perpendicular to the first direction on and electrically connected to a vertical channel of the second column of vertical channels.   
     
     
         12 . The vertical memory device of  claim 11 , wherein the bit line crosses the wiring over a vertical channel of the first column of vertical channels. 
     
     
         13 . The vertical memory device of  claim 11 , further comprising isolation patterns extending between adjacent ones of the charge storage structures on the first column of vertical channels; 
     
     
         14 . The vertical memory device of  claim 13 , wherein the gate electrodes include a ground selection line, a word line and a string selection line vertically spaced apart along the vertical channels, and wherein the isolation patterns have bottom surfaces disposed between the string selection line and the word line. 
     
     
         15 . The vertical memory device of  claim 11 , wherein the wiring is configured to apply a predetermined voltage to the first row of vertical channels, when the memory device including the channel performs a read operation, a program operation or a verification operation. 
     
     
         16 . A method of fabricating a vertical memory device, the method comprising:
 alternately forming first insulation layers and first sacrificial layers on a substrate;   forming holes through the first insulation layers and first sacrificial layers to exposed portions of the substrate, the holes including first and second columns of holes extending along a first direction parallel to the substrate;   forming a trench extending along the first direction through the first column of holes;   forming an isolation pattern in the trench and the first column of holes;   forming a charge storage structure and a vertical channel in each hole of the second column of holes;   removing the first sacrificial layers to form gaps exposing a sidewall of the charge storage structure; and   forming gate electrodes in the gaps.   
     
     
         17 . The method of  claim 16 , wherein the first and second columns of holes are offset from one another in the first direction in a zigzag pattern. 
     
     
         18 . The method of  claim 16 , wherein forming a charge storage structure and a vertical channel in each hole of the second column of holes comprises:
 sequentially forming a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern on each of inner walls of the holes of the second column of holes; and   forming a channel filling remaining portions of the holes of the second column of holes.   
     
     
         19 . The method of  claim 16 , wherein the gate electrodes include a ground selection line, a word line and a string selection line vertically spaced apart along the vertical channels, and wherein the trench has a bottom disposed between the string selection line and the word line. 
     
     
         20 . The vertical memory device of  claim 16 , wherein the bottom of the trench is disposed lower than a bottom surface of the string selection line.