Active Tiling Placement for Improved Latch-up Immunity

Abstract

A semiconductor device includes CMP dummy tiles ( 36 ) that are converted to active tiles by forming well regions ( 42 ) at a top surface of the dummy tiles, forming silicide ( 52 ) on top of the well regions, and forming, a metal interconnect structure ( 72, 82 ) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

1 - 13 . (canceled) 
     
     
         14 . An integrated circuit device, comprising:
 a semiconductor substrate in which is formed one or more trench isolation regions; and   a plurality of active tile structures disposed on the semiconductor substrate to prevent dishing from chemical mechanical polishing of the one or more trench isolation regions formed in the semiconductor substrate, where the plurality of active tile structures each comprise a highly doped region located at least at a top surface, a silicide layer formed on the highly doped region, and one or more conductive routing layers electrically connected to the silicide layer and electrically connected to a predetermined supply voltage terminal, such as a power supply or ground supply voltage terminal.   
     
     
         15 . The integrated circuit device of  claim 14 , where the semiconductor substrate comprises a p-type substrate or well, and the highly doped region comprises a P+ region which is electrically connected through the silicide layer and the one or more conductive routing layers to a ground supply voltage. 
     
     
         16 . The integrated circuit device of  claim 14 , where the semiconductor substrate comprises an n-type substrate or well, and the highly doped region comprises an N+ region which is electrically connected through the silicide layer and the one or more conductive routing layers to a power supply voltage. 
     
     
         17 . The integrated circuit device of  claim 14 , where the one or more conductive routing layers comprises:
 a conductive contact structure or via formed in a dielectric layer to contact the silicide layer; and   a supply voltage conductor layer formed over the dielectric layer to contact the conductive contact structure or via.   
     
     
         18 . The integrated circuit device of  claim 14 , further comprising one or more active circuit regions formed in the semiconductor substrate, where the plurality of active tile structures are located outside of the active circuit regions. 
     
     
         19 . The integrated circuit device of  claim 14 , further comprising a plurality of dummy tile structures disposed on the semiconductor substrate, where each dummy tile structure is not electrically connected via a top surface of the dummy tile structure to the predetermined supply voltage terminal. 
     
     
         20 . The integrated circuit device of  claim 19 , where the plurality of dummy tile structures are located to prevent dishing from chemical mechanical polishing. 
     
     
         21 . An integrated circuit, comprising:
 a semiconductor substrate of a first conductivity type comprising one or more active CMOS circuit regions and one or more non-active circuit regions adjacent to the one or more active CMOS circuit regions;   a plurality of tile structures formed in the one or more non-active circuit regions and connected to the semiconductor substrate;   one or more isolation regions formed in the one or more non-active circuit regions of the semiconductor substrate to be substantially coplanar with the plurality of tile structures; and   one or more metal interconnect structures for connecting the plurality of tile structures to a predetermined supply voltage of appropriate polarity, depending on a polarity of nearby emitters in the one or more active CMOS circuit regions, thereby providing latch-up protection.   
     
     
         22 . The integrated circuit of  claim 21 , further comprising a plurality of well tie structures of the first conductivity type formed on the plurality of tile structures. 
     
     
         23 . The integrated circuit of  claim 21 , where the one or more metal interconnect structures comprises:
 a first metal interconnect structure connected to a first plurality of well tie structures for electrically connecting a first plurality of tile structures to a first predetermined supply voltage to provide latch-up protection; and   a second metal interconnect structure connected to a second plurality of well tie structures for electrically connecting a second plurality of tile structures to a second predetermined supply voltage to provide latch-up protection.   
     
     
         24 . The integrated circuit of  claim 21 , where the semiconductor substrate comprises a p-type substrate or well, and the plurality of tile structures comprises a first plurality of highly doped P+tile structures, each of which is electrically connected through a silicide layer and one or more conductive routing layers to a ground supply voltage. 
     
     
         25 . The integrated circuit of  claim 21 , where the semiconductor substrate comprises an n-type substrate or well, and the plurality of tile structures comprises a second plurality of highly doped N+ tile structures, each of which is electrically connected through a silicide layer and one or more conductive routing layers to a power supply voltage. 
     
     
         26 . The integrated circuit of  claim 23 , where the first plurality of tile structures comprises N+ substrate regions located in close proximity to n-type emitter circuits in the one or more active CMOS circuit regions. 
     
     
         27 . The integrated circuit of  claim 23 , where the second plurality of tile structures comprises P+substrate regions located in close proximity to p-type emitter circuits in the one or more active CMOS circuit regions. 
     
     
         28 . The integrated circuit of  claim 21 , further comprising a plurality of dummy tile structures which are formed in the one or more non-active circuit regions and which are not electrically connected to a predetermined supply voltage. 
     
     
         29 . The integrated circuit of  claim 28 , where the plurality of dummy tile structures are located to prevent dishing from chemical mechanical polishing of the one or more isolation regions. 
     
     
         30 . A semiconductor device, comprising:
 a semiconductor substrate of a first conductivity type comprising one or more functional circuit regions which include parasitic NPN and PNP bipolar junction transistors inherent in CMOS structures formed in the one or more functional circuit regions;   a plurality of active tiles formed on a surface of the semiconductor substrate that are spaced apart between the one or more functional circuit regions and connected to the semiconductor substrate;   one or more chemical mechanical polished isolation regions formed on the surface of the semiconductor substrate between the one or more functional circuit regions to be substantially coplanar with the plurality of active tiles;   a first metal interconnect structure electrically connecting a first plurality of active tiles to a first predetermined supply voltage to provide latch-up protection; and   a second metal interconnect structure electrically connecting a second plurality of active tiles to a second predetermined supply voltage to provide latch-up protection.   
     
     
         31 . The semiconductor device of  claim 30 , where the first plurality of active tiles comprises N+ substrate regions located in close proximity to n-type emitter circuits in the parasitic NPN bipolar junction transistors inherent in CMOS structures formed in the one or more functional circuit regions. 
     
     
         32 . The semiconductor device of  claim 30 , where the second plurality of active tiles comprises P+ substrate regions located in close proximity to p-type emitter circuits in the parasitic PNP bipolar junction transistors inherent in CMOS structures formed in the one or more functional circuit regions. 
     
     
         33 . The semiconductor device of  claim 30 , further comprising a plurality of dummy tile structures formed on the surface of the semiconductor substrate which are spaced apart between the one or more functional circuit regions, which are located to prevent dishing from chemical mechanical polishing of the one or more chemical mechanical polished isolation regions, and which are not electrically connected to a predetermined supply voltage.