US2014281639A1PendingUtilityA1

Device power management state transition latency advertisement for faster boot time

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Assignee: WAGH MAHESHPriority: Mar 15, 2013Filed: Mar 15, 2013Published: Sep 18, 2014
Est. expiryMar 15, 2033(~6.7 yrs left)· nominal 20-yr term from priority
G06F 1/3206G06F 13/4265G06F 1/3234G06F 13/4282G06F 1/3275G06F 9/4418G06F 1/3287G06F 1/3203Y02D10/00G06F 1/3278G06F 1/325
54
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Claims

Abstract

Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.

Claims

exact text as granted — not AI-modified
1 . An apparatus comprising:
 a wait agent coupled to a storage unit to store a value to correspond to a requisite transition delay period for an exit agent to exit from a low power consumption state,   wherein the wait agent is to wait for the requisite transition delay period, in response to the wait agent determining that the exit agent has initiated its exit from the low power consumption state, before the wait agent attempts to communicate with the exit agent via a link.   
     
     
         2 . The apparatus of  claim 1 , wherein the exit agent is to write the value to the storage unit at boot time. 
     
     
         3 . The apparatus of  claim 1 , wherein the exit agent is to write the value to the storage unit via ACPI (Advanced Configuration and Power Interface). 
     
     
         4 . The apparatus of  claim 1 , wherein the exit agent is to comprise an input/output device. 
     
     
         5 . The apparatus of  claim 1 , wherein the link comprises a Peripheral Component Interconnect Express (PCIe) link. 
     
     
         6 . The apparatus of  claim 1 , wherein the low power consumption state is to comprise one of a D3 hot power state and a D3 cold power state. 
     
     
         7 . The apparatus of  claim 6 , wherein the value is about 10 ms for the D3 hot state in accordance with a PCIe standard and wherein the value is about 100 ms for the D3 cold state in accordance with a PCIe standard. 
     
     
         8 . The apparatus of  claim 1 , wherein the value is different than a transition delay period in accordance with a PCIe standard. 
     
     
         9 . The apparatus of  claim 1 , wherein the exit agent is to communicate with the wait agent in response to a request from one or more of: logic, software, firmware, PCIe bus driver, Operating System (OS), device driver and combinations thereof. 
     
     
         10 . The apparatus of  claim 1 , wherein the storage unit is to comprise one or more of: a storage device, memory, a register, a register field, a packet, a packet field, and combinations thereof. 
     
     
         11 . The apparatus of  claim 1 , wherein one or more of the wait agent, the exit agent, and the storage unit are on a same integrated circuit chip. 
     
     
         12 . An apparatus comprising:
 an exit agent to transmit a value to correspond to a requisite transition delay period for the exit agent to exit from a low power consumption state,   wherein a link, to be associated with the exit agent, is to be silent for the requisite transition delay period in response to the exit agent writing the value to the storage unit and initiating an exit from the low power consumption state.   
     
     
         13 . The apparatus of  claim 12 , wherein the exit agent is to write the value to the storage unit at boot time. 
     
     
         14 . The apparatus of  claim 12 , wherein the exit agent is to write the value to the storage unit via ACPI (Advanced Configuration and Power Interface). 
     
     
         15 . The apparatus of  claim 12 , wherein the exit agent is to comprise an input/output device. 
     
     
         16 . The apparatus of  claim 12 , wherein the link comprises a Peripheral Component Interconnect Express (PCIe) link. 
     
     
         17 . The apparatus of  claim 12 , wherein the low power consumption state is to comprise one of a D3 hot power state and a D3 cold power state. 
     
     
         18 . The apparatus of  claim 17 , wherein the value is about 10 ms for the D3 hot state in accordance with a PCIe standard and wherein the value is about 100 ms for the D3 cold state in accordance with a PCIe standard. 
     
     
         19 . The apparatus of  claim 12 , wherein the value is different than a transition delay period in accordance with a PCIe standard. 
     
     
         20 . The apparatus of  claim 12 , wherein the exit agent is to communicate with the wait agent in response to a request from one or more of: logic, software, firmware, PCIe bus driver, Operating System (OS), device driver and combinations thereof. 
     
     
         21 . The apparatus of  claim 12 , wherein the storage unit is to comprise one or more of: a storage device, memory, a register, a register field, a packet, a packet field, and combinations thereof. 
     
     
         22 . The apparatus of  claim 12 , wherein one or more of the wait agent, the exit agent, and the storage unit are on a same integrated circuit chip. 
     
     
         23 . A system comprising:
 a processor coupled to a storage unit; and   the storage unit to store a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state,   wherein the first agent is to write the value to the storage unit and wherein a second agent is to wait for the requisite transition delay period, after the first agent initiates its exit from the low power consumption state, before the second agent attempts to communicate with the first agent via a link, and   wherein one or more of the first agent, the second agent, and the storage unit are on a same integrated circuit chip.   
     
     
         24 . The system of  claim 23 , wherein the first agent is to write the value to the storage unit at boot time. 
     
     
         25 . The system of  claim 23 , wherein the first agent is to write the value to the storage unit via ACPI (Advanced Configuration and Power Interface).

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