Dynamically adaptive bit-leveling for data interfaces

Abstract

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

1 . A method for performing bit leveling for a data interface, comprising:
 receiving a pattern of alternating 1's and 0's on a data bit signal;   providing a programmable delay line for delaying the data received on the data bit signal;   strobing the data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;   incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Ta;   incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tb;   as a function of Ta and Tb, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.   
     
     
         2 . The method of  claim 1 , further comprising:
 determining the sum of Ta and Tb wherein if the sum of Ta and Tb is less than a jitter detection threshold value, adding a jitter correction offset value, and performing the method of  claim 1  again.   
     
     
         3 . The method of  claim 1 , further comprising:
 comparing Ta and Tb wherein if Ta is greater than Tb, setting the delay line delay to a value equal to the initial delay line delay with the addition of an averaging factor wherein the averaging factor is (Ta−Tb)/2.   
     
     
         4 . The method of  claim 1 , further comprising:
 comparing Ta and Tb wherein if Ta is less than Tb, setting the delay line delay to a value equal to the initial delay line delay decremented by an averaging factor wherein the averaging factor is (Tb−Ta)/2.   
     
     
         5 . A method for performing bit leveling for a data interface, comprising:
 receiving a pattern of alternating 1's and 0's on a data bit signal;   providing a programmable delay line for delaying the data received on the data bit signal;   sampling the data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;   if a sampled data bit signal differs from an expected value when first sampled from the pattern of alternating 1's and 0's, then proceeding with the following method:
 from an initial delay line delay setting, incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tc; 
 from the initial delay line delay setting, incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Td; 
 as a function of at least Tc and Td, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle. 
   
     
     
         6 . The method of  claim 5 , further comprising:
 summing Tc and Td wherein if (Tc+Td) is less than a jitter detection threshold value, adding a jitter correction offset value to the initial delay line setting, and then performing a method for performing bit leveling for a data interface, comprising:   receiving a pattern of alternating 1's and 0's on a data bit signal;
 strobing the data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing; 
   incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Ta;   incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tb;   as a function of Ta and Tb, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.   
     
     
         7 . The method of  claim 5 , further comprising:
 summing Tc and Td wherein if (Tc+Td) is less than a jitter detection threshold value, adding a jitter correction offset value to the initial delay line setting, and then re-performing the method of  claim 5 .   
     
     
         8 . The method of  claim 5 , further comprising:
 comparing the values of Tc and Td wherein if the value Tc is greater than Td, incrementally advancing DQ from the initial point until a 0 is detected, the increment for the detected 0 having been previously recorded as Td, and then further advancing DQ until a 1 is detected, whereby the delay line delay is recorded as Te;   setting the DQ delay line delay to advance DQ from the initial point by the value (Td+Te)/2.   
     
     
         9 . The method of  claim 5 , further comprising:
 Comparing the values of Tc and Td wherein if the value Tc is less than Td, incrementally delaying DQ from the initial point until a 0 is detected, the increment for the detected 0 having been previously recorded as Tc, and then further delaying DQ until a 1 is detected, whereby the delay line delay is recorded as Te;   setting the DQ delay line delay to delay DQ from the initial point by the value (Tc+Tf)/2.   
     
     
         10 . A method for performing bit leveling for a data interface, comprising:
 receiving a pattern of alternating 1's and 0's on a data bit signal;   providing a programmable delay line for delaying data received on the data bit signal to produce a delayed data bit signal;   strobing the delayed data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal value, the regular interval being at substantially the same frequency as the pattern of alternating 1's and 0's;   from an initial delay line delay setting, incrementally changing the delay line delay by a plurality of increments, and recording at each increment the sampled data bit signal value;   analyzing the recorded sampled data bit signal values to determine the width and position of strings of consecutive sampled data bits having the same signal values;   choosing a center point of one of the strings of consecutive sampled data bits to be a desired sampling point; and   setting the programmable delay line to a delay setting that causes the data strobe signal to be aligned with the desired sampling point.   
     
     
         11 . The method of  claim 10  wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the initial delay line setting. 
     
     
         12 . The method of  claim 10  wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the position of the data strobe signal. 
     
     
         13 . The method of  claim 10  wherein incrementally changing the delay line delay by a plurality of increments further comprises:
 from the initial delay line delay setting, incrementally changing the delay line delay until a criteria has been satisfied indicating the changing should terminate, and recording at each increment the sampled data bit signal value. 
 
     
     
         14 . The method of  claim 13  wherein during a first operation a first portion of the total available delay line delay is utilized, and if a suitable position for the data strobe signal to be aligned with the desired sampling point is not found, performing the operation of  claim 13  again while utilizing a portion of the total available delay line delay that is larger than the first portion. 
     
     
         15 . The method of  claim 10  wherein incrementally changing the delay line delay by a plurality of increments further comprises:
 from the initial delay line delay setting, incrementally changing the delay line delay until a maximum delay or a minimum delay provided by the delay line has been reached, and recording at each increment the sampled data bit signal value. 
 
     
     
         16 . The method of  claim 10  wherein incrementally changing the delay line delay by a plurality of increments further comprises:
 from the initial delay line delay setting, incrementally increasing the delay line delay by a first predetermined number of increments, and recording at each increment the sampled data bit signal value; and 
 from the initial delay line delay setting, incrementally decreasing the delay line delay by a second predetermined number of increments, and recording at each increment the sampled data bit signal value. 
 
     
     
         17 . The method of  claim 10  wherein choosing a center point of one of the strings of consecutive sampled data bits, further comprises choosing from strings of consecutive sampled data bits having a string length greater than a predetermined number of increments. 
     
     
         18 . The method of  claim 10  wherein at least a portion of the analyzing the recorded sampled data bit signal values is performed while incrementally changing the delay line delay. 
     
     
         19 . A circuit for implementing a dynamically configurable bit-leveling function for a data interface, comprising:
 a circuit for providing a data strobe signal;   a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit to provide a delayed data bit signal;   at least one flip-flop for sampling the delayed data bit signal;   a bit-leveling controller circuit responsive to the delayed data bit signal and for controlling the delay of the programmable delay line; and   wherein a pattern of alternating 1's and 0's is received on a data bit signal;   wherein the delayed data bit signal is sampled with the data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;   wherein the delay line delay is incrementally increased until the value of the sampled data bit signal changes, and a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at an initial delay line delay setting is stored as value Ta;   wherein the delay line delay is incrementally decreased until the value of the sampled data bit signal changes, and a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting is stored as value Tb; and   wherein as a function of Ta and Tb, the delay line setting is adjusted to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.   
     
     
         20 . The circuit of  claim 19 , wherein the circuit determines the sum of Ta and Tb, and wherein if the sum of Ta and Tb is less than a jitter detection threshold value, a jitter correction offset value is added, and the operation of the circuit per  claim 1  is performed again. 
     
     
         21 . The circuit of  claim 19 , wherein Ta and Tb are compared, and wherein if Ta is greater than Tb, the delay line delay is set to a value equal to the initial delay line delay with the addition of an averaging factor wherein the averaging factor is (Ta−Tb)/2. 
     
     
         22 . The circuit of  claim 19 , wherein Ta and Tb are compared, and wherein if Ta is less than Tb, the delay line delay is set to a value equal to the initial delay line delay decremented by an averaging factor wherein the averaging factor is (Tb−Ta)/2. 
     
     
         23 . A circuit for performing bit leveling for a data interface, comprising:
 a circuit for providing a data strobe signal;   a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit to provide a delayed data bit signal;   at least one flip-flop for sampling the delayed data bit signal;   a bit-leveling controller circuit responsive to the delayed data bit signal and for controlling the delay of the programmable delay line; and   wherein a pattern of alternating 1's and 0's is received on a data bit signal;   wherein the data bit signal is sampled with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;   wherein, if a sampled data bit signal differs from an expected value when first sampled from the pattern of alternating 1's and 0's, the circuit is operated according to the following method:
 from an initial delay line delay setting, incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tc; 
 from the initial delay line delay setting, incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Td; 
 as a function of at least Tc and Td, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle. 
   
     
     
         24 . The circuit of  claim 23  wherein Tc and Td are summed, and wherein if (Tc+Td) is less than a jitter detection threshold value, a jitter correction offset value is added to the initial delay line setting, and the circuit is further operated according to a method for performing bit leveling for a data interface, comprising:
 receiving a pattern of alternating 1's and 0's on a data bit signal; 
 strobing the data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing; 
 incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Ta; 
 incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tb; 
 as a function of Ta and Tb, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle. 
 
     
     
         25 . The circuit of  claim 23  wherein Tc and Td are summed, and wherein if (Tc+Td) is less than a jitter detection threshold value, a jitter correction offset value is added to the initial delay line setting, and the method of  claim 5  is performed again. 
     
     
         26 . The circuit of  claim 23 , wherein the values of Tc and Td are compared, and wherein if the value Tc is greater than Td, DQ is incrementally advanced from the initial point until a 0 is detected, the increment for the detected 0 having been previously recorded as Td, and then DQ is further advanced until a 1 is detected, whereby the delay line delay is recorded as Te; and
 wherein the DQ delay line delay is set to advance DQ from the initial point by the value (Td+Te)/2.   
     
     
         27 . The circuit of  claim 23 , wherein the values of Tc and Td are compared and wherein if the value Tc is less than Td, DQ is incrementally delayed from the initial point until a 0 is detected, the increment for the detected 0 having been previously recorded as Tc, and then DQ is further delayed until a 1 is detected, whereby the delay line delay is recorded as Te; and
 wherein the DQ delay line delay is set to delay DQ from the initial point by the value (Tc+Tf)/2.   
     
     
         28 . A circuit for performing bit leveling for a data interface, comprising:
 a circuit for providing a data strobe signal;   a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit to provide a delayed data bit signal;   at least one flip-flop for sampling the delayed data bit signal;   a bit-leveling controller circuit responsive to the delayed data bit signal and for controlling the delay of the programmable delay line; and   wherein a pattern of alternating 1's and 0's is received on a data bit signal;   wherein the delayed data bit signal is sampled with a data strobe signal at a regular interval to produce a sampled data bit signal value, the regular interval being at substantially the same frequency as the pattern of alternating 1's and 0's;   wherein from an initial delay line delay setting, the delay line delay is incrementally changed by a plurality of increments, and at each increment the sampled data bit signal value is recorded;   wherein the recorded sampled data bit signal values are analyzed to determine the width and position of strings of consecutive sampled data bits having the same signal values;   wherein a center point of one of the strings of consecutive sampled data bits is chosen to be a desired sampling point; and   wherein the programmable delay line is set to a delay setting that causes the data strobe signal to be aligned with the desired sampling point.   
     
     
         29 . The circuit of  claim 28  wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the initial delay line setting. 
     
     
         30 . The circuit of  claim 28  wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the position of the data strobe signal. 
     
     
         31 . The circuit of  claim 28  wherein incrementally changing the delay line delay by a plurality of increments further comprises:
 from the initial delay line delay setting, incrementally changing the delay line delay until a criteria has been satisfied indicating the changing should terminate, and recording at each increment the sampled data bit signal value. 
 
     
     
         32 . The circuit of  claim 31  wherein during a first operation a first portion of the total available delay line delay is utilized, and if a suitable position for the data strobe signal to be aligned with the desired sampling point is not found, the operation of  claim 31  is performed again while utilizing a portion of the total available delay line delay that is larger than the first portion. 
     
     
         33 . The circuit of  claim 28  wherein incrementally changing the delay line delay by a plurality of increments further comprises:
 from the initial delay line delay setting, incrementally changing the delay line delay until a maximum delay or a minimum delay provided by the delay line has been reached, and recording at each increment the sampled data bit signal value. 
 
     
     
         34 . The circuit of  claim 28  wherein incrementally changing the delay line delay by a plurality of increments further comprises:
 from the initial delay line delay setting, incrementally increasing the delay line delay by a first predetermined number of increments, and recording at each increment the sampled data bit signal value; and 
 from the initial delay line delay setting, incrementally decreasing the delay line delay by a second predetermined number of increments, and recording at each increment the sampled data bit signal value. 
 
     
     
         35 . The circuit of  claim 28  wherein choosing a center point of one of the strings of consecutive sampled data bits, further comprises choosing from strings of consecutive sampled data bits having a string length greater than a predetermined number of increments. 
     
     
         36 . The circuit of  claim 28  wherein at least a portion of the analyzing the recorded sampled data bit signal values is performed while incrementally changing the delay line delay.