US2014289094A1PendingUtilityA1

Wire Speed Monitoring and Control of Electronic Financial Transactions

Assignee: DEUTSCHE BANK AGPriority: Nov 19, 2010Filed: Jun 5, 2014Published: Sep 25, 2014
Est. expiryNov 19, 2030(~4.3 yrs left)· nominal 20-yr term from priority
G06Q 40/04
53
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Claims

Abstract

An in-line hardware message filter device inspects incoming securities transactions. The invention is implemented as an integrated circuit (IC) device which contains computer code in the form of on-chip hardware instructions. Data messages comprising orders enter the device in exchange-specific formats. Messages that satisfy pre-determined risk assessment filters are allowed to pass through the device to the appropriate securities exchange for execution. The system functions as a passive device for all legitimate network traffic passing directly or indirectly between a customer's computer and a securities exchange's order-acceptance computer. Advantageously, the invention allows the broker-dealer to check and pass messages or orders as they come through the system without having to store the full message before making a risk assessment decision. The hardware-only nature of the invention serves to maximize the speed of order validation and to perform pre-trade checks in a cut-through or store-and-forward mode.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A reprogammable integrated circuit (IC) device comprising embedded hardware instructions for performing risk assessment of a securities transaction, the instructions coding for a method comprising the steps of:
 a) receiving by the IC device an incoming order for the securities transaction;   b) parsing the order by the IC device into a plurality of order components;   c) evaluating by the IC device one or more order components in accordance with pre-established criteria; and   d1) if the order components pass the pre-established criteria, permitting the order to pass to a securities exchange for subsequent handling; or   d2) if the order components do not pass the pre-established criteria, truncating the order before passing the order to a securities exchange.   
     
     
         2 . The IC device according to  claim 1 , wherein the device is an FPGA, PAL, PLA, or CPLD device. 
     
     
         3 . The IC device according to  claim 1 , wherein the device can handle a throughput of about 500,000 incoming orders per second and support a minimum of about 30 TCP sessions. 
     
     
         4 . The IC device according to  claim 1 , wherein the device is reprogrammable locally or remotely. 
     
     
         5 . The IC device according to  claim 1 , wherein the pre-established criteria comprise one or more risk management criteria selected from the group consisting of a restricted securities trading list; minimum or maximum order size; minimum or maximum order dollar value; minimum or maximum notional value; order type; broker identification;
 and securities or currency settings.   
     
     
         6 . The IC device according to  claim 1 , wherein the device further comprises embedded hardware instructions to periodically receive updated pre-established criteria. 
     
     
         7 . The IC device according to  claim 1 , wherein the device further comprises embedded hardware instructions for logging inspected orders. 
     
     
         8 . The IC device according to  claim 1 , wherein the incoming order enters the device in an exchange-specific format. 
     
     
         9 . The IC device according to  claim 8 , wherein the format is FIX OUCH, or ArcaDirect. 
     
     
         10 . The IC device according to  claim 1 , wherein the device further comprises embedded hardware instructions for completely truncating an order before the order can pass to the securities exchange. 
     
     
         11 . The IC device according to  claim 1 , wherein the device further comprises embedded hardware instructions for blocking a session due to a securities breach or a transaction failing one or more criteria. 
     
     
         12 . A method for performing risk assessment of a securities transaction using a reprogrammable integrated circuit (IC) device containing embedded hardware instructions for performing the method, the method comprising the steps of:
 a) forwarding to the IC device an order for the securities transaction;   b) parsing the order by the IC device into a plurality of order components;   c) evaluating by the IC device one or more order components in accordance with pre-established criteria; and   d1) if the order components pass the pre-established criteria, permitting the order to pass to a securities exchange for subsequent handling; or   d2) if the order components do not pass the pre-established criteria, truncating the order before passing the order to a securities exchange.   
     
     
         13 . The method according to  claim 12 , wherein the IC device is an FPGA, PAL, PLA, or CPLD device.

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