Memory controller, semiconductor memory apparatus and decoding method

Abstract

A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

1 - 16 . (canceled) 
     
     
         17 . A memory controller comprising:
 an operation section configured to decode coded data through iterative processing in which column processing and row processing are repeatedly performed; and   a memory section configured to store the coded data read out from a non-volatile semiconductor memory section and store information which is being subjected to the iterative processing and is outputted from the operation section.   
     
     
         18 . The memory controller according to  claim 17 , wherein the non-volatile semiconductor memory section is a NAND type flash memory section. 
     
     
         19 . The memory controller according to  claim 17 , wherein the operation section performs decoding through partial parallel processing. 
     
     
         20 . A semiconductor memory apparatus, comprising:
 a non-volatile semiconductor memory section; and   a memory controller including:
 an operation section configured to decode coded data through iterative processing in which column processing and row processing are repeatedly performed, and 
 a memory section configured to store the coded data read out is being subjected to the iterative processing and is outputted from the operation section. 
   
     
     
         21 . The semiconductor memory apparatus according to  claim 20 , wherein the non-volatile semiconductor memory section is a NAND type flash memory section. 
     
     
         22 . The semiconductor memory apparatus according to  claim 20 , wherein the operation section performs decoding through partial parallel processing. 
     
     
         23 . A method of decoding coded data, the method comprising:
 storing coded data read out from a non-volatile semiconductor memory section is stored in a memory section of a memory controller; and   decoding, by an operation section, the coded data stored in the memory section through iterative processing in which column processing and row processing are repeatedly performed, the iterative processing being performed by storing, in the memory section, information which is being subjected to the iterative processing and is outputted from the operation section, and using the information read out from the memory section.   
     
     
         24 . The decoding method according to  claim 23 , wherein the non-volatile semiconductor memory section is a NAND type flash memory section. 
     
     
         25 . The decoding method according to  claim 23 , wherein the decoding is performed through partial parallel processing.