Graphics processing architecture employing a unified shader

Abstract

A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

What is claimed is: 
     
         1 . A graphics processor, comprising:
 an arbiter circuit for selecting one of a plurality of inputs in response to a control signal; and   a unified shader, including means for performing vertex operations and pixel operations, and performing one of the vertex operations or pixel operations based on selected one of a plurality of inputs of an arbiter circuit.