Methods for implementing variable speed scan testing

Abstract

In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.

1 . A method for designing an integrated circuit comprising:
 developing a first design for an integrated circuit;   simulating scan tests for the integrated circuit at multiple predetermined test clock frequencies using the first design, wherein the simulation includes a simulation of a test clock generator whose test clock frequency is responsive to m bits of a test vector; and   developing a second design for the integrated circuit responsive to the simulation of the scan test.   
     
     
         2 . The method of  claim 1  wherein the first design is an RTL design. 
     
     
         3 . The method of  claim 1 , wherein the first design is a gate-level design. 
     
     
         4 . The method of  claim 1 , wherein the first design is a logic-level design. 
     
     
         5 . The method of  claim 1 , wherein the second design is a gate-level design. 
     
     
         6 . The method of  claim 1 , wherein the second design is a logic-level design. 
     
     
         7 . The method of  claim 1 , wherein the simulation of the scan test is responsive to n bits of the test vector. 
     
     
         8 . The method of  claim 1 , further comprising:
 generating a first set of test vectors configured to be simulated using a first predetermined test clock frequency;   simulating the integrated circuit using the first set of test vectors responsive to the first predetermined test clock frequency;   identifying a first set of outlier cells of the integrated circuit responsive to the simulation of the integrated circuit;   generating a second set of test vectors responsive to the identified outlier cells, wherein the second set of test vectors is configured to operate at a second test clock frequency.   
     
     
         9 . The method of  claim 8 , wherein outlier cells include cells that have been over-tested. 
     
     
         10 . The method of  claim 8 , wherein outlier cells include cells that have been under-tested. 
     
     
         11 . A method for designing an integrated circuit comprising:
 developing a first design for an integrated circuit at a first type of synthesis;   developing a second design for the integrated circuit at a second type of synthesis, wherein the first and second designs correspond to the same functionality of the integrated circuit;   simulating a scan test for the integrated circuit at a test clock frequency using the second design, wherein the simulation includes a simulation of a test clock generator whose test clock frequency is responsive to m bits of a test vector; and   developing a third design for the integrated circuit at a first type of synthesis responsive to the simulation of the scan test.   
     
     
         12 . The method of  claim 11 , wherein the first type of synthesis is RTL synthesis. 
     
     
         13 . The method of  claim 11 , wherein the second type of synthesis is gate-level synthesis. 
     
     
         14 . The method of  claim 11 , wherein the simulation of the scan test is responsive to n bits of the test vector. 
     
     
         15 . The method of  claim 11 , further comprising a fourth design for the integrated circuit at a second type of synthesis responsive to the simulation of the scan test. 
     
     
         16 . The method of  claim 11 , further comprising a fourth design for the integrated circuit at a second type of synthesis that corresponds to the third design. 
     
     
         17 . A method for designing an integrated circuit comprising:
 developing a first design for an integrated circuit;   manufacturing the integrated circuit, wherein the first design and the integrated circuit have corresponding functionality;   testing the integrated circuit using a scan test at a test clock frequency, wherein the a test clock generator generates a signal at the test clock frequency responsive to m bits of a test vector; and   developing a second design for the integrated circuit responsive to results of the scan test.   
     
     
         18 . The method of  claim 17 , wherein the first design is a gate-level design. 
     
     
         19 . The method of  claim 17 , wherein the second design is a gate-level design. 
     
     
         20 . The method of  claim 17 , wherein the simulation of the scan test is responsive to n bits of the test vector. 
     
     
         21 . The method of  claim 17 , further comprising a third design for the integrated circuit responsive to the second design.