High-Speed Current Steering Logic Output Buffer

Abstract

A current steering logic buffer for generating an output clock signal, comprises: a buffer for receiving an input clock signal; a current source; switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and a feedback loop for controlling the current source as a function of the outputs and a reference voltage.

We claim:  
     
         1 . A current steering logic buffer for generating an output clock signal, comprising:
 a buffer for receiving an input clock signal;   a current source;   switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and   a feedback loop for controlling the current source as a function of the outputs and a reference voltage.   
     
     
         2 . The current steering logic buffer of  claim 1  wherein the feedback loop comprises an operational amplifier, and wherein the operational amplifier compares the reference voltage and a sampled voltage from the outputs to control the current source. 
     
     
         3 . The current steering logic buffer of  claim 2  further comprising a sampling circuit for generating the sampled voltage. 
     
     
         4 . The current steering logic buffer of  claim 3  wherein the sampling circuit comprises serially-connected resistors connected across the outputs and serially-connected capacitors connected across the outputs, and wherein the serially-connected resistors and the serially-connected capacitors have a common node for determining the sampled voltage. 
     
     
         5 . The current steering logic buffer of  claim 4  wherein the common node is connected to a capacitor for stabilizing the sampled voltage. 
     
     
         6 . The current steering logic buffer of  claim 1  wherein the input clock signal is a differential signal in accordance with current mode logic levels. 
     
     
         7 . The current steering logic buffer of  claim 1  wherein the output clock signal is a differential signal in accordance with high-speed current steering logic (“HCSL”) levels. 
     
     
         8 . The current steering logic buffer of  claim 7  wherein the output clock signal supports multiple HCSL levels by setting the reference voltage to one or more predefined voltages. 
     
     
         9 . The current steering logic buffer of  claim 1  wherein the buffer has a first buffer output and a second buffer output, wherein the switches comprise a first switch and a second switch, wherein the first buffer output is connected to the first switch, and wherein the second buffer output is connected to the second switch. 
     
     
         10 . The current steering logic buffer of  claim 1  wherein the logic buffer further comprising a band gap voltage generator to generate the internally-generated reference voltage. 
     
     
         11 . A current steering logic buffer for generating an output clock signal for PCI-Express applications, comprising:
 a buffer for receiving an input clock signal, wherein the input clock signal is a differential signal in accordance with current mode logic levels;   a current source;   switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal and wherein the output clock signal is a differential signal in accordance with high-speed current steering logic (“HCSL”) levels; and   a feedback loop for controlling the current source as a function of the outputs and an internally generated reference voltage,   wherein the feedback loop comprises an operational amplifier, and   wherein the operational amplifier compares the reference voltage and a sampled voltage from the outputs to control the current source.   
     
     
         12 . The current steering logic buffer of  claim 11  further comprising a sampling circuit for generating the sampled voltage. 
     
     
         13 . The current steering logic buffer of  claim 12  wherein the sampling circuit comprises serially-connected resistors connected across the outputs and serially-connected capacitors connected across the outputs, and wherein the serially-connected resistors and the serially-connected capacitors have a common node for determining the sampled voltage. 
     
     
         14 . The current steering logic buffer of  claim 13  wherein the common node is connected to a capacitor for stabilizing the sampled voltage. 
     
     
         15 . The current steering logic buffer of  claim 11  wherein the output clock signal supports multiple HCSL levels by setting the reference voltage to one or more predefined voltages. 
     
     
         16 . The current steering logic buffer of  claim 11  wherein the buffer has a first buffer output and a second buffer output, wherein the switches comprise a first switch and a second switch, wherein the first buffer output is connected to the first switch, and wherein the second buffer output is connected to the second switch. 
     
     
         17 . The current steering logic buffer of  claim 11  wherein the logic buffer further comprising a band gap voltage generator to generate the internally-generated reference voltage. 
     
     
         18 . A current steering logic buffer for generating an output clock signal for PCI-Express applications, comprising:
 a buffer for receiving an input clock signal, wherein the input clock signal is a differential signal in accordance with current mode logic levels;   a current source;   switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal, wherein the output clock signal is a differential signal in accordance with high-speed current steering logic (“HCSL”) levels, and wherein the output clock signal supports multiple HCSL levels by setting the reference voltage to one or more predefined voltages;   a feedback loop for controlling the current source as a function of the outputs and an internally generated reference voltage; and   a sampling circuit for generating the sampled voltage, wherein the sampling circuit comprises serially-connected resistors connected across the outputs and serially-connected capacitors connected across the outputs, wherein the serially-connected resistors and the serially-connected capacitors have a common node for determining the sampled voltage, and wherein the common node is connected to a capacitor for stabilizing the sampled voltage,   wherein the feedback loop comprises an operational amplifier, and   wherein the operational amplifier compares the reference voltage and the sampled voltage from the outputs to control the current source.   
     
     
         19 . The current steering logic buffer of  claim 18  wherein the buffer has a first buffer output and a second buffer output, wherein the switches comprise a first switch and a second switch, wherein the first buffer output is connected to the first switch, and wherein the second buffer output is connected to the second switch. 
     
     
         20 . The current steering logic buffer of  claim 18  wherein the logic buffer further comprising a band gap voltage generator to generate the internally-generated reference voltage.