Fractional phase locked loop having an exact output frequency and phase and method of using the same

Abstract

A fractional-N frequency synthesizer having an exact output frequency and phase includes a phase locked loop including a phase detector responsive to a reference signal and a fractional divider. The phase locked loop has an output signal whose frequency is a fractional multiple of the input reference signal. The synthesizer also includes a modulator having a modulus for providing an output to the fractional divider, in which the modulus multiplied by the ratio of the frequency of the output signal to the frequency of the reference signal is a non-integer number.

1 . A fractional-N frequency synthesizer having an exact output frequency and phase, the synthesizer comprising:
 a phase locked loop including a phase detector responsive to a reference signal and a fractional divider, said phase locked loop having an output signal whose input frequency is a fractional multiple of the input reference signal; and   a modulator having a modulus for providing an output to the fractional divider, in which the modulus multiplied by the ratio of the frequency of the output signal to the frequency of the reference signal is a non-integer number.   
     
     
         2 . The synthesizer of  claim 1  in which the modulator is implemented by a look up table. 
     
     
         3 . The synthesizer of  claim 1  in which the modulator is a delta-sigma modulator having a phase accumulator. 
     
     
         4 . The synthesizer of  claim 3  in which the delta-sigma modulator is a higher order delta-sigma modulator having a plurality of accumulators including the phase accumulator. 
     
     
         5 . The synthesizer of  claim 4  further including a greatest common divisor (GCD) counter clocked at an input reference signal or a submultiple thereof. 
     
     
         6 . The synthesizer of  claim 5 , in which an output of the GCD counter is used to only reset the phase accumulator in the delta-sigma modulator to its initial seed value, thus setting the long-term phase to a predetermined value and achieving reduced spurious. 
     
     
         7 . The synthesizer of  claim 5 , in which an output of the GCD counter is used to reset all the accumulators in the modulator and to reset the phase accumulator to the initial seed value, thus setting the longer-term phase to an exact predetermined value. 
     
     
         8 . The synthesizer of  claim 4  in which the modulator accumulates the fractional value based upon a power of two modulus such that the rate of phase accumulation in the modulator is near but not equal to the desired output phase. 
     
     
         9 . The synthesizer of  claim 5  in which the GCD reset instant is synchronized to the next nearest modulator clock edge. 
     
     
         10 . The synthesizer of  claim 5  in which if the original phase is desired immediately after returning to a previous output frequency, and all output frequencies are related by the GCD interval, then the phase accumulator is loaded immediately with a new seed number calculated by multiplying the desired frequency by a reference counter, to provide a number modulo of a GCD value, scaled to the modulus of the binary accumulator, and added to the original seed value. 
     
     
         11 . The synthesizer of  claim 3  further including a synchronizer responsive to the GCD counter and a clock of the modulator for crossing the clock domains of the gcd counter and the modulator clock.